From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 2/4] clk: renesas: r9a07g043: Add RSPI clock and reset entries
Date: Sun, 1 May 2022 09:34:48 +0100 [thread overview]
Message-ID: <20220501083450.26541-3-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220501083450.26541-1-biju.das.jz@bp.renesas.com>
Add RSPI{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 57b9eb9e0d2b..21cf82ad7de3 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -230,6 +230,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x588, 0),
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
0x588, 1),
+ DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
+ 0x590, 0),
+ DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
+ 0x590, 1),
+ DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
+ 0x590, 2),
DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
0x594, 0),
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
@@ -271,6 +277,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
+ DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
+ DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
+ DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
--
2.25.1
next prev parent reply other threads:[~2022-05-01 8:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-01 8:34 [PATCH 0/4] Add RZ/G2UL CLK and Reset entries for RSPI,TSU,ADC and SPI Multi IO Bus Controller Biju Das
2022-05-01 8:34 ` [PATCH 1/4] clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O " Biju Das
2022-05-02 15:28 ` Geert Uytterhoeven
2022-05-01 8:34 ` Biju Das [this message]
2022-05-02 15:29 ` [PATCH 2/4] clk: renesas: r9a07g043: Add RSPI clock and reset entries Geert Uytterhoeven
2022-05-01 8:34 ` [PATCH 3/4] clk: renesas: r9a07g043: Add TSU clock and reset entry Biju Das
2022-05-02 15:29 ` Geert Uytterhoeven
2022-05-01 8:34 ` [PATCH 4/4] clk: renesas: r9a07g043: Add clock and reset entries for ADC Biju Das
2022-05-02 15:30 ` Geert Uytterhoeven
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