All of lore.kernel.org
 help / color / mirror / Atom feed
From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH 05/16] drm/i915: Drop has_psr_hw_tracking from device info
Date: Sat,  7 May 2022 06:28:39 -0700	[thread overview]
Message-ID: <20220507132850.10272-5-jose.souza@intel.com> (raw)
In-Reply-To: <20220507132850.10272-1-jose.souza@intel.com>

No need to have this parameter in intel_device_info struct
as this feature was only supported by display 9, 10 and 11, tigerlake
and DG1, no newer platforms will have this feature.

While at it also moving it to intel_psr.c as this is the only place
were it is used.

As a side effect of the of removal this flag, it will not be printed
in dmesg during driver load anymore and developers will have to rely
on to check the macro and compare with platform being used and IP
versions of it.

v2:
- moved macro to intel_psr.c

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
 drivers/gpu/drm/i915/i915_drv.h          | 2 --
 drivers/gpu/drm/i915/i915_pci.c          | 5 -----
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 4 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 06db407e2749f..9521360440748 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -84,6 +84,11 @@
  * use page flips.
  */
 
+#define HAS_PSR_HW_TRACKING(dev_priv) ((DISPLAY_VER(dev_priv) >= 9 && \
+					DISPLAY_VER(dev_priv) <= 11) || \
+					IS_TIGERLAKE(dev_priv) || \
+					IS_DG1(dev_priv))
+
 static bool psr_global_enabled(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 27dccddfadd84..98160fe2bc074 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1308,8 +1308,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DP_MST(dev_priv)		 (HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9)
-#define HAS_PSR_HW_TRACKING(dev_priv) \
-	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 41bcc692e54c7..00c61e3b49c97 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -629,7 +629,6 @@ static const struct intel_device_info chv_info = {
 	GEN9_DEFAULT_PAGE_SIZES, \
 	.display.has_dmc = 1, \
 	.display.has_hdcp = 1, \
-	.display.has_psr_hw_tracking = 1, \
 	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 	.dbuf.slice_mask = BIT(DBUF_S1)
 
@@ -677,7 +676,6 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_fpga_dbg = 1, \
 	.display.fbc_mask = BIT(INTEL_FBC_A), \
 	.display.has_hdcp = 1, \
-	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_dmc = 1, \
 	.has_rps = true, \
@@ -863,7 +861,6 @@ static const struct intel_device_info rkl_info = {
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 		BIT(TRANSCODER_C),
 	.display.has_hti = 1,
-	.display.has_psr_hw_tracking = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
@@ -894,7 +891,6 @@ static const struct intel_device_info adl_s_info = {
 	PLATFORM(INTEL_ALDERLAKE_S),
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.display.has_hti = 1,
-	.display.has_psr_hw_tracking = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.dma_mask_size = 39,
@@ -952,7 +948,6 @@ static const struct intel_device_info adl_p_info = {
 			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 	.display.has_cdclk_crawl = 1,
 	.display.has_modular_fia = 1,
-	.display.has_psr_hw_tracking = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 5bc866de9b17c..5a39e42029877 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -173,7 +173,6 @@ enum intel_ppgtt_type {
 	func(has_hti); \
 	func(has_modular_fia); \
 	func(has_overlay); \
-	func(has_psr_hw_tracking); \
 	func(overlay_needs_physical); \
 	func(supports_tv);
 
-- 
2.36.0


  parent reply	other threads:[~2022-05-07 13:29 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-07 13:28 [Intel-gfx] [PATCH 01/16] drm/i915: Drop has_llc from device info José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 02/16] drm/i915: Drop has_ipc " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 03/16] drm/i915/display: Disable DSB for DG2 and Alderlake-P José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 04/16] drm/i915: Drop has_rc6p from device info José Roberto de Souza
2022-05-07 13:28 ` José Roberto de Souza [this message]
2022-05-07 13:28 ` [Intel-gfx] [PATCH 06/16] drm/i915: Drop supports_tv " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 07/16] drm/i915: Drop has_4tile " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 08/16] drm/i915: Drop has_64bit_reloc " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 09/16] drm/i915: Drop has_global_mocs " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 10/16] drm/i915: Drop has_guc_deprivilege " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 11/16] drm/i915: Drop has_pxp " José Roberto de Souza
2022-05-07 18:05   ` kernel test robot
2022-05-07 19:47   ` kernel test robot
2022-05-07 13:28 ` [Intel-gfx] [PATCH 12/16] drm/i915: Drop has_heci_gscfi " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 13/16] " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 14/16] drm/i915: Drop has_runtime_pm " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 15/16] drm/i915: Drop has_logical_ring_contexts " José Roberto de Souza
2022-05-07 13:28 ` [Intel-gfx] [PATCH 16/16] drm/i915: Drop display.has_fpga_db " José Roberto de Souza
2022-05-09 12:38   ` Joonas Lahtinen
2022-05-09 14:19     ` Souza, Jose
2022-05-10  6:25       ` Joonas Lahtinen
2022-05-10  7:41         ` Jani Nikula
2022-05-11  7:39           ` Tvrtko Ursulin
2022-05-11 13:56             ` Souza, Jose
2022-05-07 13:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/16] drm/i915: Drop has_llc " Patchwork
2022-05-07 13:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-07 13:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-07 15:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-09 11:09 ` [Intel-gfx] [PATCH 01/16] " Matthew Auld
2022-05-09 14:05   ` Souza, Jose
2022-05-09 14:52     ` Matthew Auld
2022-05-09 14:55       ` Souza, Jose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220507132850.10272-5-jose.souza@intel.com \
    --to=jose.souza@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.