[Intel-gfx] [PATCH 3/7] drm/i915/dg2: DG2 MBD config

From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com
Subject: [Intel-gfx] [PATCH 3/7] drm/i915/dg2: DG2 MBD config
Date: Wed, 18 May 2022 18:37:12 +0530	[thread overview]
Message-ID: <20220518130716.10936-4-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20220518130716.10936-1-anshuman.gupta@intel.com>

Add DG2 Motherboard Down Config check support.

BSpec: 44477
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.h               | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 3dcd54517b89..dec7628522c5 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1271,6 +1271,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private *i915)
 
 	if (IS_DG1(i915))
 		return intel_opregion_dg1_mbd_config(i915);
+	else if (IS_DG2_MBD(i915))
+		return true;
 
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10f273800645..c5ecc490dced 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1071,6 +1071,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+/*
+ * FIXME: Need to define a new SUBPLATFORM INTEL_SUBPLATFORM_DG2_MBD
+ * for PCI id range 5690..5695, but G10, G11 SUBPLATFROM conflicts
+ * with those pci id range.
+ */
+#define DG2_MBD_CONFIG_MASK	GENMASK(7, 4)
+#define DG2_MBD_CONFIG_VAL	FIELD_PREP(DG2_MBD_CONFIG_MASK, 9)
+#define IS_DG2_MBD(dev_priv) (IS_DG2(dev_priv) && \
+			      (INTEL_DEVID(dev_priv) & DG2_MBD_CONFIG_MASK) == DG2_MBD_CONFIG_VAL)
 #define IS_ADLS_RPLS(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(dev_priv) \
-- 
2.26.2

