From: "Víctor Colombo" <victor.colombo@eldorado.org.br>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au,
groug@kaod.org, richard.henderson@linaro.org,
victor.colombo@eldorado.org.br
Subject: [PATCH v2 04/11] target/ppc: Move mffsl to decodetree
Date: Mon, 23 May 2022 14:58:00 -0300 [thread overview]
Message-ID: <20220523175807.59333-5-victor.colombo@eldorado.org.br> (raw)
In-Reply-To: <20220523175807.59333-1-victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fp-impl.c.inc | 38 +++++++++++++-----------------
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b7bd17e4d1..68ea34d608 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -326,6 +326,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
+MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
### Decimal Floating-Point Arithmetic Instructions
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 531e8b8796..e602cbf0a5 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -607,28 +607,6 @@ static void gen_mffs(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
-/* mffsl */
-static void gen_mffsl(DisasContext *ctx)
-{
- TCGv_i64 t0;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- /* Mask everything except mode, status, and enables. */
- tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
- set_fpr(rD(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
{
TCGv_i64 fpscr = tcg_temp_new_i64();
@@ -713,6 +691,22 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
return true;
}
+static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
+{
+ TCGv_i64 fpscr;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ gen_reset_fpstatus();
+ fpscr = place_from_fpscr(a->rt,
+ FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN);
+
+ tcg_temp_free_i64(fpscr);
+
+ return true;
+}
+
/* mtfsb0 */
static void gen_mtfsb0(DisasContext *ctx)
{
diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
index c4865da63f..f7ca1cc8b8 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -76,8 +76,6 @@ GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
-GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
- PPC2_ISA300),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
--
2.25.1
next prev parent reply other threads:[~2022-05-23 18:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 17:57 [PATCH v2 00/11] BCDA and mffscdrn implementations Víctor Colombo
2022-05-23 17:57 ` [PATCH v2 01/11] target/ppc: Fix insn32.decode style issues Víctor Colombo
2022-05-23 17:57 ` [PATCH v2 02/11] target/ppc: Move mffscrn[i] to decodetree Víctor Colombo
2022-05-23 17:57 ` [PATCH v2 03/11] target/ppc: Move mffsce " Víctor Colombo
2022-05-23 17:58 ` Víctor Colombo [this message]
2022-05-23 17:58 ` [PATCH v2 05/11] target/ppc: Move mffs[.] " Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 06/11] target/ppc: Implement mffscdrn[i] instructions Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 07/11] tests/tcg/ppc64: Add mffsce test Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 08/11] target/ppc: Add flag for ISA v2.06 BCDA instructions Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 09/11] target/ppc: implement addg6s Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 10/11] target/ppc: implement cbcdtd Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 11/11] target/ppc: implement cdtbcd Víctor Colombo
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