From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Anup Patel <apatel@ventanamicro.com>,
Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
Date: Thu, 26 May 2022 15:35:34 +0530 [thread overview]
Message-ID: <20220526100536.49672-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220526100536.49672-1-apatel@ventanamicro.com>
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4d04b20d06..4a55c6a709 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -159,6 +159,9 @@
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
+/* Machine Counter Setup */
+#define CSR_MCOUNTINHIBIT 0x320
+
/* 32-bit only */
#define CSR_MSTATUSH 0x310
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6dbe9b541f..409a209f14 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore,
+ .min_priv_ver = PRIV_VERSION_1_11_0 },
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
--
2.34.1
next prev parent reply other threads:[~2022-05-26 10:13 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-26 10:05 [PATCH v3 0/4] QEMU RISC-V nested virtualization fixes Anup Patel
2022-05-26 10:05 ` [PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest Anup Patel
2022-05-26 10:05 ` Anup Patel [this message]
2022-05-26 10:05 ` [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Anup Patel
2022-06-06 1:48 ` Alistair Francis
2022-06-06 1:53 ` Alistair Francis
2022-06-07 3:01 ` Anup Patel
2022-06-07 3:04 ` Anup Patel
2022-05-26 10:05 ` [PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match Anup Patel
2022-06-06 1:55 ` Alistair Francis
2022-06-07 2:50 ` Anup Patel
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