[Intel-gfx] [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vbt

From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, Nischal Varide <nischal.varide@intel.com>
Subject: [Intel-gfx] [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vbt
Date: Thu,  2 Jun 2022 19:48:50 +0530	[thread overview]
Message-ID: <20220602141850.21301-6-animesh.manna@intel.com> (raw)
In-Reply-To: <20220602141850.21301-1-animesh.manna@intel.com>

From: Nischal Varide <nischal.varide@intel.com>

Tigerlake and newer has two instances of PPS, to support up to two
eDP panels.

Signed-off-by: Nischal Varide <nischal.varide@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 1b21a341962f..52cb5be4e901 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -365,7 +365,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+	    DISPLAY_VER(dev_priv) >= 12)
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
-- 
2.29.0

