From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com,
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, jerry.zuo@amd.com,
Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH 03/16] Revert "drm/amd/display: Pass the new context into disable OTG WA"
Date: Fri, 3 Jun 2022 16:11:34 -0400 [thread overview]
Message-ID: <20220603201147.121817-4-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20220603201147.121817-1-hamza.mahfooz@amd.com>
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
This reverts commit 25b1b4128c75bc9b9cf033425427d085f97439ec.
Causes a hang when hotplugging DP, shutting down system, or
enabling dual eDP.
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 8 ++++----
.../drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 8 ++++----
.../drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 6a81c1aea0be..bca5f01da763 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -99,13 +99,13 @@ static int dcn31_get_active_display_cnt_wa(
return display_count;
}
-static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
+static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
@@ -211,11 +211,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
- dcn31_disable_otg_wa(clk_mgr_base, context, true);
+ dcn31_disable_otg_wa(clk_mgr_base, true);
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
- dcn31_disable_otg_wa(clk_mgr_base, context, false);
+ dcn31_disable_otg_wa(clk_mgr_base, false);
update_dispclk = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index aa01a18df419..fb4ae800e919 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -79,13 +79,13 @@ static int dcn315_get_active_display_cnt_wa(
return display_count;
}
-static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
+static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
@@ -173,11 +173,11 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
- dcn315_disable_otg_wa(clk_mgr_base, context, true);
+ dcn315_disable_otg_wa(clk_mgr_base, true);
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
- dcn315_disable_otg_wa(clk_mgr_base, context, false);
+ dcn315_disable_otg_wa(clk_mgr_base, false);
update_dispclk = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 7192f30858eb..e4bb9c6193b5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -112,13 +112,13 @@ static int dcn316_get_active_display_cnt_wa(
return display_count;
}
-static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
+static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
@@ -221,11 +221,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
- dcn316_disable_otg_wa(clk_mgr_base, context, true);
+ dcn316_disable_otg_wa(clk_mgr_base, true);
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
- dcn316_disable_otg_wa(clk_mgr_base, context, false);
+ dcn316_disable_otg_wa(clk_mgr_base, false);
update_dispclk = true;
}
--
2.36.1
next prev parent reply other threads:[~2022-06-03 20:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-03 20:11 [PATCH 00/16] DC Patches May 30, 2022 Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 01/16] drm/amd/display: Update optimized blank calc and programming Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 02/16] drm/amd/display: Detect dpcd_rev when hotplug mst monitor Hamza Mahfooz
2022-06-03 20:11 ` Hamza Mahfooz [this message]
2022-06-03 20:11 ` [PATCH 04/16] drm/amd/display: Blank eDP on enable drv if odm enabled Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 05/16] drm/amd/display: Correct min comp buffer size Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 06/16] drm/amd/display: add DP sanity checks during enable stream Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 07/16] drm/amd/display: Cap OLED brightness per max frame-average luminance Hamza Mahfooz
2022-06-08 10:02 ` Aaron Ma
2022-06-08 19:02 ` Li, Roman
2022-06-03 20:11 ` [PATCH 08/16] drm/amd/display: Enable 3 plane MPO Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 09/16] drm/amd/display: [FW Promotion] Release 0.0.119.0 Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 10/16] drm/amd/display: 3.2.188 Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 11/16] drm/amd/display: Fix dpp dto for disabled pipes Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 12/16] drm/amd/display: Fix entry into transient encoder assignment mode Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 13/16] drm/amd/display: Avoid reading LTTPR caps in non-LTTPR mode Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 14/16] drm/amd/display: Extend soc BB capabilitiy Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 15/16] drm/amd/display: Add HDMI member to DTO Hamza Mahfooz
2022-06-03 20:11 ` [PATCH 16/16] drm/amd/display: 3.2.189 Hamza Mahfooz
2022-06-06 13:38 ` [PATCH 00/16] DC Patches May 30, 2022 Wheeler, Daniel
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