From: Maxime Ripard <maxime@cerno.tech>
To: Daniel Vetter <daniel.vetter@intel.com>,
David Airlie <airlied@linux.ie>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Maxime Ripard <maxime@cerno.tech>
Cc: dri-devel@lists.freedesktop.org,
Dave Stevenson <dave.stevenson@raspberrypi.com>
Subject: [PATCH 15/33] drm/vc4: dsi: Fix dsi0 interrupt support
Date: Mon, 13 Jun 2022 16:47:42 +0200 [thread overview]
Message-ID: <20220613144800.326124-16-maxime@cerno.tech> (raw)
In-Reply-To: <20220613144800.326124-1-maxime@cerno.tech>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
DSI0 seemingly had very little or no testing as a load of
the register mappings were incorrect/missing, so host
transfers always timed out due to enabling/checking incorrect
bits in the interrupt enable and status registers.
Fixes: 4078f5757144 ("drm/vc4: Add DSI driver")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_dsi.c | 111 ++++++++++++++++++++++++++--------
1 file changed, 85 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 97a258c934af..333ea96fcde4 100644
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
@@ -181,8 +181,50 @@
#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
-#define DSI0_INT_STAT 0x24
-#define DSI0_INT_EN 0x28
+#define DSI0_INT_STAT 0x24
+#define DSI0_INT_EN 0x28
+# define DSI0_INT_FIFO_ERR BIT(25)
+# define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23)
+# define DSI0_INT_CMDC_DONE_SHIFT 23
+# define DSI0_INT_CMDC_DONE_NO_REPEAT 1
+# define DSI0_INT_CMDC_DONE_REPEAT 3
+# define DSI0_INT_PHY_DIR_RTF BIT(22)
+# define DSI0_INT_PHY_D1_ULPS BIT(21)
+# define DSI0_INT_PHY_D1_STOP BIT(20)
+# define DSI0_INT_PHY_RXLPDT BIT(19)
+# define DSI0_INT_PHY_RXTRIG BIT(18)
+# define DSI0_INT_PHY_D0_ULPS BIT(17)
+# define DSI0_INT_PHY_D0_LPDT BIT(16)
+# define DSI0_INT_PHY_D0_FTR BIT(15)
+# define DSI0_INT_PHY_D0_STOP BIT(14)
+/* Signaled when the clock lane enters the given state. */
+# define DSI0_INT_PHY_CLK_ULPS BIT(13)
+# define DSI0_INT_PHY_CLK_HS BIT(12)
+# define DSI0_INT_PHY_CLK_FTR BIT(11)
+/* Signaled on timeouts */
+# define DSI0_INT_PR_TO BIT(10)
+# define DSI0_INT_TA_TO BIT(9)
+# define DSI0_INT_LPRX_TO BIT(8)
+# define DSI0_INT_HSTX_TO BIT(7)
+/* Contention on a line when trying to drive the line low */
+# define DSI0_INT_ERR_CONT_LP1 BIT(6)
+# define DSI0_INT_ERR_CONT_LP0 BIT(5)
+/* Control error: incorrect line state sequence on data lane 0. */
+# define DSI0_INT_ERR_CONTROL BIT(4)
+# define DSI0_INT_ERR_SYNC_ESC BIT(3)
+# define DSI0_INT_RX2_PKT BIT(2)
+# define DSI0_INT_RX1_PKT BIT(1)
+# define DSI0_INT_CMD_PKT BIT(0)
+
+#define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \
+ DSI0_INT_ERR_CONTROL | \
+ DSI0_INT_ERR_CONT_LP0 | \
+ DSI0_INT_ERR_CONT_LP1 | \
+ DSI0_INT_HSTX_TO | \
+ DSI0_INT_LPRX_TO | \
+ DSI0_INT_TA_TO | \
+ DSI0_INT_PR_TO)
+
# define DSI1_INT_PHY_D3_ULPS BIT(30)
# define DSI1_INT_PHY_D3_STOP BIT(29)
# define DSI1_INT_PHY_D2_ULPS BIT(28)
@@ -892,6 +934,9 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
DSI_PORT_WRITE(PHY_AFEC0, afec0);
+ /* AFEC reset hold time */
+ mdelay(1);
+
DSI_PORT_WRITE(PHY_AFEC1,
VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
@@ -1058,12 +1103,9 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
/* Bring AFE out of reset. */
- if (dsi->variant->port == 0) {
- } else {
- DSI_PORT_WRITE(PHY_AFEC0,
- DSI_PORT_READ(PHY_AFEC0) &
- ~DSI1_PHY_AFEC0_RESET);
- }
+ DSI_PORT_WRITE(PHY_AFEC0,
+ DSI_PORT_READ(PHY_AFEC0) &
+ ~DSI_PORT_BIT(PHY_AFEC0_RESET));
vc4_dsi_ulps(dsi, false);
@@ -1182,13 +1224,28 @@ static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
/* Enable the appropriate interrupt for the transfer completion. */
dsi->xfer_result = 0;
reinit_completion(&dsi->xfer_completion);
- DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
- if (msg->rx_len) {
- DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
- DSI1_INT_PHY_DIR_RTF));
+ if (dsi->variant->port == 0) {
+ DSI_PORT_WRITE(INT_STAT,
+ DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);
+ if (msg->rx_len) {
+ DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |
+ DSI0_INT_PHY_DIR_RTF));
+ } else {
+ DSI_PORT_WRITE(INT_EN,
+ (DSI0_INTERRUPTS_ALWAYS_ENABLED |
+ VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,
+ DSI0_INT_CMDC_DONE)));
+ }
} else {
- DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
- DSI1_INT_TXPKT1_DONE));
+ DSI_PORT_WRITE(INT_STAT,
+ DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
+ if (msg->rx_len) {
+ DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
+ DSI1_INT_PHY_DIR_RTF));
+ } else {
+ DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
+ DSI1_INT_TXPKT1_DONE));
+ }
}
/* Send the packet. */
@@ -1205,7 +1262,7 @@ static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
ret = dsi->xfer_result;
}
- DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
+ DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
if (ret)
goto reset_fifo_and_return;
@@ -1251,7 +1308,7 @@ static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
DSI_PORT_BIT(CTRL_RESET_FIFOS));
DSI_PORT_WRITE(TXPKT1C, 0);
- DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
+ DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
return ret;
}
@@ -1388,26 +1445,28 @@ static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
DSI_PORT_WRITE(INT_STAT, stat);
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
+ DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
+ DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_ERR_CONT_LP0, "LP0 contention");
+ DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_ERR_CONT_LP1, "LP1 contention");
+ DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_HSTX_TO, "HSTX timeout");
+ DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_LPRX_TO, "LPRX timeout");
+ DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_TA_TO, "turnaround timeout");
+ DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");
dsi_handle_error(dsi, &ret, stat,
- DSI1_INT_PR_TO, "peripheral reset timeout");
+ DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");
- if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
+ if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
+ DSI0_INT_CMDC_DONE_MASK) |
+ DSI_PORT_BIT(INT_PHY_DIR_RTF))) {
complete(&dsi->xfer_completion);
ret = IRQ_HANDLED;
- } else if (stat & DSI1_INT_HSTX_TO) {
+ } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {
complete(&dsi->xfer_completion);
dsi->xfer_result = -ETIMEDOUT;
ret = IRQ_HANDLED;
--
2.36.1
next prev parent reply other threads:[~2022-06-13 14:48 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-13 14:47 [PATCH 00/33] drm/vc4: Misc fixes Maxime Ripard
2022-06-13 14:47 ` [PATCH 01/33] drm/vc4: drv: Adopt the dma configuration from the HVS or V3D component Maxime Ripard
2022-06-13 14:47 ` Maxime Ripard
2022-06-13 14:47 ` [PATCH 02/33] drm/vc4: kms: Warn if clk_set_min_rate fails Maxime Ripard
2022-06-28 11:28 ` Dave Stevenson
2022-06-13 14:47 ` [PATCH 03/33] drm/vc4: kms: Use maximum FIFO load for the HVS clock rate Maxime Ripard
2022-06-28 11:30 ` Dave Stevenson
2022-06-13 14:47 ` [PATCH 04/33] drm/vc4: plane: Remove subpixel positioning check Maxime Ripard
2022-06-13 14:47 ` [PATCH 05/33] drm/vc4: plane: Fix margin calculations for the right/bottom edges Maxime Ripard
2022-06-13 14:47 ` [PATCH 06/33] drm/vc4: plane: Add alpha_blend_mode property to each plane Maxime Ripard
2022-06-13 14:47 ` [PATCH 07/33] drm/vc4: hvs: Add debugfs node that dumps the current display lists Maxime Ripard
2022-06-13 14:47 ` [PATCH 08/33] drm/vc4: dpi: Add support for composite syncs to vc4_dpi Maxime Ripard
2022-06-13 14:47 ` [PATCH 09/33] drm/vc4: dpi: Add option for inverting pixel clock and output enable Maxime Ripard
2022-06-13 14:47 ` [PATCH 10/33] drm/vc4: dpi: Ensure a default format is selected Maxime Ripard
2022-06-13 14:47 ` [PATCH 11/33] drm/vc4: dsi: Release workaround buffer and DMA Maxime Ripard
2022-06-13 14:47 ` [PATCH 12/33] drm/vc4: dsi: Correct DSI divider calculations Maxime Ripard
2022-06-13 14:47 ` [PATCH 13/33] drm/vc4: dsi: Correct pixel order for DSI0 Maxime Ripard
2022-06-13 14:47 ` [PATCH 14/33] drm/vc4: dsi: Register dsi0 as the correct vc4 encoder type Maxime Ripard
2022-06-13 14:47 ` Maxime Ripard [this message]
2022-06-13 14:47 ` [PATCH 16/33] drm/vc4: dsi: Add correct stop condition to vc4_dsi_encoder_disable iteration Maxime Ripard
2022-06-13 14:47 ` [PATCH 17/33] drm/vc4: hdmi: Disable audio if dmas property is present but empty Maxime Ripard
2022-06-13 14:47 ` Maxime Ripard
2022-06-13 14:47 ` [PATCH 18/33] drm/vc4: hdmi: Add all the vc5 HDMI registers into the debugfs dumps Maxime Ripard
2022-06-13 14:47 ` [PATCH 19/33] drm/vc4: hdmi: Clear unused infoframe packet RAM registers Maxime Ripard
2022-06-13 14:47 ` [PATCH 20/33] drm/vc4: hdmi: Avoid full hdmi audio fifo writes Maxime Ripard
2022-06-13 14:47 ` [PATCH 21/33] drm/vc4: hdmi: Reset HDMI MISC_CONTROL register Maxime Ripard
2022-06-13 14:47 ` [PATCH 22/33] drm/vc4: hdmi: Switch to pm_runtime_status_suspended Maxime Ripard
2022-06-13 14:47 ` [PATCH 23/33] drm/vc4: hdmi: Move HDMI reset to pm_resume Maxime Ripard
2022-08-04 23:11 ` Florian Fainelli
2022-08-09 19:02 ` Florian Fainelli
2022-08-10 11:06 ` Dave Stevenson
2022-08-10 20:33 ` Stefan Wahren
2022-08-15 14:12 ` Maxime Ripard
2022-08-15 16:52 ` Florian Fainelli
2022-08-18 15:38 ` Maxime Ripard
2022-08-09 20:16 ` Stefan Wahren
2022-08-09 20:28 ` Florian Fainelli
2022-06-13 14:47 ` [PATCH 24/33] drm/vc4: hdmi: Stop checking for enabled output in audio Maxime Ripard
2022-06-13 14:47 ` [PATCH 25/33] drm/vc4: hdmi: Skip writes to disabled packet RAM Maxime Ripard
2022-06-13 14:47 ` [PATCH 26/33] drm/vc4: hdmi: Remove VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT Maxime Ripard
2022-06-13 14:47 ` [PATCH 27/33] drm/vc4: hdmi: Add HDMI format detection registers to register list Maxime Ripard
2022-06-13 14:47 ` [PATCH 28/33] drm/vc4: hdmi: Add MISC_CONTROL register for vc4 Maxime Ripard
2022-06-13 14:47 ` [PATCH 29/33] drm/vc4: hdmi: Report that 3d/stereo is allowed Maxime Ripard
2022-06-13 14:47 ` [PATCH 30/33] drm/vc4: hdmi: Fix timings for interlaced modes Maxime Ripard
2022-06-13 14:47 ` [PATCH 31/33] drm/vc4: hdmi: Force modeset when bpc or format changes Maxime Ripard
2022-06-13 14:47 ` [PATCH 32/33] drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes Maxime Ripard
2022-06-13 14:48 ` [PATCH 33/33] drm/vc4: hdmi: Move pixel doubling from Pixelvalve to HDMI block Maxime Ripard
2022-06-28 13:34 ` [PATCH 00/33] drm/vc4: Misc fixes Maxime Ripard
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220613144800.326124-16-maxime@cerno.tech \
--to=maxime@cerno.tech \
--cc=airlied@linux.ie \
--cc=daniel.vetter@intel.com \
--cc=dave.stevenson@raspberrypi.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=tzimmermann@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.