From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com
Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v3 01/13] PCI: Add PCI_EXP_LNKCAP_MLW macros
Date: Fri, 1 Jul 2022 17:54:08 +0900 [thread overview]
Message-ID: <20220701085420.870306-2-yoshihiro.shimoda.uh@renesas.com> (raw)
In-Reply-To: <20220701085420.870306-1-yoshihiro.shimoda.uh@renesas.com>
Add macros defining Maximum Link Width bits in Link Capabilities
Register.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
include/uapi/linux/pci_regs.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 108f8523fa04..c619b108df06 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -538,6 +538,13 @@
#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
#define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
+#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
+#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
+#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
+#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
+#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
+#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
+#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
--
2.25.1
next prev parent reply other threads:[~2022-07-01 8:55 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-01 8:54 [PATCH v3 00/13] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2022-07-01 8:54 ` Yoshihiro Shimoda [this message]
2022-07-01 8:54 ` [PATCH v3 02/13] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 03/13] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 04/13] PCI: dwc: Add reset_all_bars flag Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 05/13] PCI: dwc: endpoint: Read num-lanes property before ep_pre_init() Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 06/13] PCI: dwc: host: Read num-lanes property before host_init() Yoshihiro Shimoda
2022-07-11 18:33 ` Rob Herring
2022-07-12 1:32 ` Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 07/13] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2022-07-11 19:05 ` Rob Herring
2022-07-01 8:54 ` [PATCH v3 08/13] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2022-07-11 19:06 ` Rob Herring
2022-07-01 8:54 ` [PATCH v3 09/13] PCI: renesas: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2022-07-01 14:57 ` Geert Uytterhoeven
2022-07-08 11:25 ` Yoshihiro Shimoda
2022-07-19 13:25 ` Geert Uytterhoeven
2022-07-21 2:29 ` Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 10/13] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2022-07-01 14:58 ` Geert Uytterhoeven
2022-07-01 8:54 ` [PATCH v3 11/13] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 12/13] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2022-07-01 8:54 ` [PATCH v3 13/13] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
2022-07-08 11:34 ` [PATCH v3 00/13] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
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