From: Johan Hovold <johan+linaro@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Felipe Balbi <balbi@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Wesley Cheng <quic_wcheng@quicinc.com>,
linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Johan Hovold <johan+linaro@kernel.org>
Subject: [PATCH 7/7] arm64: dts: qcom: reorder USB interrupts
Date: Wed, 13 Jul 2022 15:13:40 +0200 [thread overview]
Message-ID: <20220713131340.29401-8-johan+linaro@kernel.org> (raw)
In-Reply-To: <20220713131340.29401-1-johan+linaro@kernel.org>
Three SoCs did not follow the interrupt order specified by the USB
controller binding.
While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 10 ++++++----
arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++--------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++--------
3 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 7a193678b4f5..8daefd50217a 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -372,11 +372,13 @@ usb: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 19 IRQ_TYPE_EDGE_BOTH>,
<&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 18 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "ss_phy_irq", "dm_hs_phy_irq";
+ <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
power-domains = <&gcc USB30_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7ac8aa110f81..65be7f3ec74c 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3026,11 +3026,13 @@ usb_1: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "dm_hs_phy_irq", "ss_phy_irq";
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -3081,11 +3083,13 @@ usb_2: usb@a8f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "dm_hs_phy_irq", "ss_phy_irq";
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 65c7fe54613d..e72a04411888 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2461,11 +2461,13 @@ usb_1: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "dm_hs_phy_irq", "ss_phy_irq";
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -2509,11 +2511,13 @@ usb_2: usb@a8f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
- "dm_hs_phy_irq", "ss_phy_irq";
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
--
2.35.1
next prev parent reply other threads:[~2022-07-13 13:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 13:13 [PATCH 0/7] usb: dwc3: add support for SC8280XP Johan Hovold
2022-07-13 13:13 ` [PATCH 1/7] dt-bindings: usb: qcom,dwc3: add SC8280XP binding Johan Hovold
2022-07-14 10:48 ` Krzysztof Kozlowski
2022-07-14 10:51 ` Krzysztof Kozlowski
2022-07-13 13:13 ` [PATCH 2/7] dt-bindings: usb: qcom,dwc3: refine interrupt requirements Johan Hovold
2022-07-14 10:50 ` Krzysztof Kozlowski
2022-07-13 13:13 ` [PATCH 3/7] usb: dwc3: qcom: fix missing optional irq warnings Johan Hovold
2022-07-13 14:00 ` Andrew Halaney
2022-07-13 13:13 ` [PATCH 4/7] arm64: dts: qcom: sc8280xp: fix USB clock order Johan Hovold
2022-07-14 10:52 ` Krzysztof Kozlowski
2022-07-13 13:13 ` [PATCH 5/7] arm64: dts: qcom: sc8280xp: fix USB interrupts Johan Hovold
2022-07-13 14:12 ` Andrew Halaney
2022-07-13 14:35 ` Johan Hovold
2022-07-13 14:43 ` Andrew Halaney
2022-07-13 15:03 ` Johan Hovold
2022-07-14 10:52 ` Krzysztof Kozlowski
2022-07-13 13:13 ` [PATCH 6/7] arm64: dts: qcom: sc7280: reorder " Johan Hovold
2022-07-14 10:54 ` Krzysztof Kozlowski
2022-07-13 13:13 ` Johan Hovold [this message]
2022-07-14 10:54 ` [PATCH 7/7] arm64: dts: qcom: " Krzysztof Kozlowski
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