From: Xiaoyao Li <xiaoyao.li@intel.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Isaku Yamahata" <isaku.yamahata@gmail.com>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Cornelia Huck" <cohuck@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Laszlo Ersek" <lersek@redhat.com>,
"Eric Blake" <eblake@redhat.com>
Cc: Connor Kuehl <ckuehl@redhat.com>,
erdemaktas@google.com, kvm@vger.kernel.org,
qemu-devel@nongnu.org, seanjc@google.com, xiaoyao.li@intel.com
Subject: [PATCH v1 35/40] hw/i386: add option to forcibly report edge trigger in acpi tables
Date: Tue, 2 Aug 2022 15:47:45 +0800 [thread overview]
Message-ID: <20220802074750.2581308-36-xiaoyao.li@intel.com> (raw)
In-Reply-To: <20220802074750.2581308-1-xiaoyao.li@intel.com>
From: Isaku Yamahata <isaku.yamahata@intel.com>
When level trigger isn't supported on x86 platform,
forcibly report edge trigger in acpi tables.
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
hw/i386/acpi-build.c | 99 ++++++++++++++++++++++++++++---------------
hw/i386/acpi-common.c | 50 ++++++++++++++++------
2 files changed, 104 insertions(+), 45 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0355bd3ddaad..83d4777ca9ad 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -894,7 +894,8 @@ static void build_dbg_aml(Aml *table)
aml_append(table, scope);
}
-static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
+static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg,
+ bool level_trigger_unsupported)
{
Aml *dev;
Aml *crs;
@@ -906,7 +907,10 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
crs = aml_resource_template();
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
+ AML_ACTIVE_HIGH,
AML_SHARED, irqs, ARRAY_SIZE(irqs)));
aml_append(dev, aml_name_decl("_PRS", crs));
@@ -930,7 +934,8 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
return dev;
}
-static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
+static Aml *build_gsi_link_dev(const char *name, uint8_t uid,
+ uint8_t gsi, bool level_trigger_unsupported)
{
Aml *dev;
Aml *crs;
@@ -943,7 +948,10 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
crs = aml_resource_template();
irqs = gsi;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
+ AML_ACTIVE_HIGH,
AML_SHARED, &irqs, 1));
aml_append(dev, aml_name_decl("_PRS", crs));
@@ -962,7 +970,7 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
}
/* _CRS method - get current settings */
-static Aml *build_iqcr_method(bool is_piix4)
+static Aml *build_iqcr_method(bool is_piix4, bool level_trigger_unsupported)
{
Aml *if_ctx;
uint32_t irqs;
@@ -970,7 +978,9 @@ static Aml *build_iqcr_method(bool is_piix4)
Aml *crs = aml_resource_template();
irqs = 0;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
aml_append(method, aml_name_decl("PRR0", crs));
@@ -1004,7 +1014,7 @@ static Aml *build_irq_status_method(void)
return method;
}
-static void build_piix4_pci0_int(Aml *table)
+static void build_piix4_pci0_int(Aml *table, bool level_trigger_unsupported)
{
Aml *dev;
Aml *crs;
@@ -1025,12 +1035,16 @@ static void build_piix4_pci0_int(Aml *table)
aml_append(sb_scope, field);
aml_append(sb_scope, build_irq_status_method());
- aml_append(sb_scope, build_iqcr_method(true));
+ aml_append(sb_scope, build_iqcr_method(true, level_trigger_unsupported));
- aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
- aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
- aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
- aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"),
+ level_trigger_unsupported));
dev = aml_device("LNKS");
{
@@ -1039,7 +1053,9 @@ static void build_piix4_pci0_int(Aml *table)
crs = aml_resource_template();
irqs = 9;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
AML_ACTIVE_HIGH, AML_SHARED,
&irqs, 1));
aml_append(dev, aml_name_decl("_PRS", crs));
@@ -1125,7 +1141,7 @@ static Aml *build_q35_routing_table(const char *str)
return pkg;
}
-static void build_q35_pci0_int(Aml *table)
+static void build_q35_pci0_int(Aml *table, bool level_trigger_unsupported)
{
Aml *field;
Aml *method;
@@ -1177,25 +1193,41 @@ static void build_q35_pci0_int(Aml *table)
aml_append(sb_scope, field);
aml_append(sb_scope, build_irq_status_method());
- aml_append(sb_scope, build_iqcr_method(false));
+ aml_append(sb_scope, build_iqcr_method(false, level_trigger_unsupported));
- aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
- aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
- aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
- aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
- aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
- aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
- aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
- aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"),
+ level_trigger_unsupported));
- aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
- aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
- aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
- aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
- aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
- aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
- aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
- aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
+ aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17,
+ level_trigger_unsupported));
aml_append(table, sb_scope);
}
@@ -1440,6 +1472,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
X86MachineState *x86ms = X86_MACHINE(machine);
+ bool level_trigger_unsupported = x86ms->eoi_intercept_unsupported;
AcpiMcfgInfo mcfg;
bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
uint32_t nr_mem = machine->ram_slots;
@@ -1474,7 +1507,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
- build_piix4_pci0_int(dsdt);
+ build_piix4_pci0_int(dsdt, level_trigger_unsupported);
} else {
sb_scope = aml_scope("_SB");
dev = aml_device("PCI0");
@@ -1522,7 +1555,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
if (pm->pcihp_bridge_en) {
build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
- build_q35_pci0_int(dsdt);
+ build_q35_pci0_int(dsdt, level_trigger_unsupported);
if (pcms->smbus) {
build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC);
}
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c
index 4aaafbdd7b5d..485fc17816be 100644
--- a/hw/i386/acpi-common.c
+++ b/hw/i386/acpi-common.c
@@ -105,6 +105,7 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev);
AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = oem_id,
.oem_table_id = oem_table_id };
+ bool level_trigger_unsupported = x86ms->eoi_intercept_unsupported;
acpi_table_begin(&table, table_data);
/* Local APIC Address */
@@ -124,18 +125,43 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
IO_APIC_SECONDARY_ADDRESS, IO_APIC_SECONDARY_IRQBASE);
}
- if (x86ms->apic_xrupt_override) {
- build_xrupt_override(table_data, 0, 2,
- 0 /* Flags: Conforms to the specifications of the bus */);
- }
-
- for (i = 1; i < 16; i++) {
- if (!(x86ms->pci_irq_mask & (1 << i))) {
- /* No need for a INT source override structure. */
- continue;
- }
- build_xrupt_override(table_data, i, i,
- 0xd /* Flags: Active high, Level Triggered */);
+ if (level_trigger_unsupported) {
+ /* Force edge trigger */
+ if (x86ms->apic_xrupt_override) {
+ build_xrupt_override(table_data, 0, 2,
+ /* Flags: active high, edge triggered */
+ 1 | (1 << 2));
+ }
+
+ for (i = x86ms->apic_xrupt_override ? 1 : 0; i < 16; i++) {
+ build_xrupt_override(table_data, i, i,
+ /* Flags: active high, edge triggered */
+ 1 | (1 << 2));
+ }
+
+ if (x86ms->ioapic2) {
+ for (i = 0; i < 16; i++) {
+ build_xrupt_override(table_data, IO_APIC_SECONDARY_IRQBASE + i,
+ IO_APIC_SECONDARY_IRQBASE + i,
+ /* Flags: active high, edge triggered */
+ 1 | (1 << 2));
+ }
+ }
+ } else {
+ if (x86ms->apic_xrupt_override) {
+ build_xrupt_override(table_data, 0, 2,
+ 0 /* Flags: Conforms to the specifications of the bus */);
+ }
+
+ for (i = 1; i < 16; i++) {
+ if (!(x86ms->pci_irq_mask & (1 << i))) {
+ /* No need for a INT source override structure. */
+ continue;
+ }
+ build_xrupt_override(table_data, i, i,
+ 0xd /* Flags: Active high, Level Triggered */);
+
+ }
}
if (x2apic_mode) {
--
2.27.0
next prev parent reply other threads:[~2022-08-02 7:51 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-02 7:47 [PATCH v1 00/40] TDX QEMU support Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 01/40] *** HACK *** linux-headers: Update headers to pull in TDX API changes Xiaoyao Li
2022-08-02 9:47 ` Daniel P. Berrangé
2022-08-02 10:38 ` Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 02/40] i386: Introduce tdx-guest object Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 03/40] target/i386: Implement mc->kvm_type() to get VM type Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 04/40] target/i386: Introduce kvm_confidential_guest_init() Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 05/40] i386/tdx: Implement tdx_kvm_init() to initialize TDX VM context Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 06/40] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES Xiaoyao Li
2022-08-25 10:12 ` Gerd Hoffmann
2022-08-25 15:35 ` Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 07/40] i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object Xiaoyao Li
2022-08-25 10:16 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 08/40] i386/tdx: Adjust the supported CPUID based on TDX restrictions Xiaoyao Li
2022-08-03 7:33 ` Chenyi Qiang
2022-08-04 0:55 ` Xiaoyao Li
2022-08-26 4:00 ` Xiaoyao Li
2022-08-25 11:26 ` Gerd Hoffmann
2022-08-25 12:44 ` Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 09/40] i386/tdx: Update tdx_fixed0/1 bits by tdx_caps.cpuid_config[] Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 10/40] i386/tdx: Integrate tdx_caps->xfam_fixed0/1 into tdx_cpuid_lookup Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 11/40] i386/tdx: Integrate tdx_caps->attrs_fixed0/1 to tdx_cpuid_lookup Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 12/40] i386/kvm: Move architectural CPUID leaf generation to separate helper Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 13/40] KVM: Introduce kvm_arch_pre_create_vcpu() Xiaoyao Li
2022-08-25 11:28 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 14/40] i386/tdx: Initialize TDX before creating TD vcpus Xiaoyao Li
2022-08-25 11:29 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 15/40] i386/tdx: Add property sept-ve-disable for tdx-guest object Xiaoyao Li
2022-08-25 11:36 ` Gerd Hoffmann
2022-08-25 14:42 ` Xiaoyao Li
2022-08-26 5:57 ` Gerd Hoffmann
2022-09-02 2:33 ` Xiaoyao Li
2022-09-02 2:52 ` Sean Christopherson
2022-09-02 5:46 ` Gerd Hoffmann
2022-09-02 15:26 ` Sean Christopherson
2022-09-02 16:52 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 16/40] i386/tdx: Wire CPU features up with attributes of TD guest Xiaoyao Li
2022-08-25 11:38 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 17/40] i386/tdx: Validate TD attributes Xiaoyao Li
2022-08-25 11:39 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 18/40] i386/tdx: Implement user specified tsc frequency Xiaoyao Li
2022-08-25 11:41 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 19/40] i386/tdx: Set kvm_readonly_mem_enabled to false for TDX VM Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 20/40] i386/tdvf: Introduce function to parse TDVF metadata Xiaoyao Li
2022-08-26 9:12 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 21/40] i386/tdx: Parse TDVF metadata for TDX VM Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 22/40] i386/tdx: Skip BIOS shadowing setup Xiaoyao Li
2022-08-26 9:13 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 23/40] i386/tdx: Don't initialize pc.rom for TDX VMs Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 24/40] i386/tdx: Track mem_ptr for each firmware entry of TDVF Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 25/40] i386/tdx: Track RAM entries for TDX VM Xiaoyao Li
2022-08-26 9:15 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 26/40] headers: Add definitions from UEFI spec for volumes, resources, etc Xiaoyao Li
2022-08-26 9:19 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 27/40] i386/tdx: Setup the TD HOB list Xiaoyao Li
2022-08-26 10:27 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 28/40] i386/tdx: Add TDVF memory via KVM_TDX_INIT_MEM_REGION Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 29/40] i386/tdx: Call KVM_TDX_INIT_VCPU to initialize TDX vcpu Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 30/40] i386/tdx: Finalize TDX VM Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 31/40] i386/tdx: Disable SMM for TDX VMs Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 32/40] i386/tdx: Disable PIC " Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 33/40] i386/tdx: Don't allow system reset " Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 34/40] hw/i386: add eoi_intercept_unsupported member to X86MachineState Xiaoyao Li
2022-08-26 10:32 ` Gerd Hoffmann
2022-08-02 7:47 ` Xiaoyao Li [this message]
2022-08-26 10:32 ` [PATCH v1 35/40] hw/i386: add option to forcibly report edge trigger in acpi tables Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 36/40] i386/tdx: Don't synchronize guest tsc for TDs Xiaoyao Li
2022-08-26 10:33 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 37/40] i386/tdx: Only configure MSR_IA32_UCODE_REV in kvm_init_msrs() " Xiaoyao Li
2022-08-02 7:47 ` [PATCH v1 38/40] i386/tdx: Skip kvm_put_apicbase() " Xiaoyao Li
2022-08-26 10:34 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 39/40] i386/tdx: Don't get/put guest state for TDX VMs Xiaoyao Li
2022-08-26 10:35 ` Gerd Hoffmann
2022-08-02 7:47 ` [PATCH v1 40/40] docs: Add TDX documentation Xiaoyao Li
2022-08-26 10:36 ` Gerd Hoffmann
2022-08-02 9:49 ` [PATCH v1 00/40] TDX QEMU support Daniel P. Berrangé
2022-08-02 10:55 ` Xiaoyao Li
2022-08-03 17:44 ` Daniel P. Berrangé
2022-08-05 0:16 ` Xiaoyao Li
2022-09-05 0:58 ` Xiaoyao Li
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