All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org
Cc: "Daniel Henrique Barboza" <danielhb413@gmail.com>,
	qemu-devel@nongnu.org, "BALATON Zoltan" <balaton@eik.bme.hu>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model
Date: Mon,  8 Aug 2022 12:27:20 +0200	[thread overview]
Message-ID: <20220808102734.133084-9-clg@kaod.org> (raw)
In-Reply-To: <20220808102734.133084-1-clg@kaod.org>

The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.

Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.

The DCR device inherits from SysBus because most of these devices also
have a MMIO regions and/or IRQs. Being a SysBusDevice makes things
easier to install the device model in the overall SoC.

The "cpu" link should be considered as modeling the piece of HW logic
connecting the device to the DCR bus.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/ppc4xx.h | 17 +++++++++++++++
 hw/ppc/ppc4xx_devs.c    | 46 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)

diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 021376c2d260..bb373db0ba10 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -27,6 +27,7 @@
 
 #include "hw/ppc/ppc.h"
 #include "exec/memory.h"
+#include "hw/sysbus.h"
 
 /* PowerPC 4xx core initialization */
 void ppc4xx_reset(void *opaque);
@@ -50,4 +51,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
 
 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
 
+/*
+ * Generic DCR device
+ */
+#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
+struct Ppc4xxDcrDeviceState {
+    SysBusDevice parent_obj;
+
+    PowerPCCPU *cpu;
+};
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
+                         dcr_read_cb dcr_read, dcr_write_cb dcr_write);
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+                        Error **errp);
+
 #endif /* PPC4XX_H */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f20098cf417c..e07bdba0f912 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -696,3 +696,49 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
                          mal, &dcr_read_mal, &dcr_write_mal);
     }
 }
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
+                         dcr_read_cb dcr_read, dcr_write_cb dcr_write)
+{
+    CPUPPCState *env;
+
+    assert(dev->cpu);
+
+    env = &dev->cpu->env;
+
+    ppc_dcr_register(env, dcrn, dev, dcr_read, dcr_write);
+}
+
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+                        Error **errp)
+{
+    object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+    return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
+}
+
+
+static Property ppc4xx_dcr_properties[] = {
+    DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
+                     PowerPCCPU *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->user_creatable = false;
+    device_class_set_props(dc, ppc4xx_dcr_properties);
+}
+
+static const TypeInfo ppc4xx_types[] = {
+    {
+        .name           = TYPE_PPC4xx_DCR_DEVICE,
+        .parent         = TYPE_SYS_BUS_DEVICE,
+        .instance_size  = sizeof(Ppc4xxDcrDeviceState),
+        .class_init     = ppc4xx_dcr_class_init,
+        .abstract       = true,
+    }
+};
+
+DEFINE_TYPES(ppc4xx_types)
-- 
2.37.1



  parent reply	other threads:[~2022-08-08 10:43 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-08 10:27 [PATCH v3 00/22] ppc: QOM'ify 405 board Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 01/22] ppc/ppc405: Remove taihu machine Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 02/22] ppc/ppc405: Introduce a PPC405 generic machine Cédric Le Goater
2022-08-08 12:23   ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 03/22] ppc/ppc405: Move devices under the ref405ep machine Cédric Le Goater
2022-08-08 12:23   ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 04/22] ppc/ppc405: Move SRAM " Cédric Le Goater
2022-08-08 12:25   ` BALATON Zoltan
2022-08-08 13:38     ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 05/22] ppc/ppc405: Introduce a PPC405 SoC Cédric Le Goater
2022-08-08 12:43   ` BALATON Zoltan
2022-08-08 13:51     ` Cédric Le Goater
2022-08-08 14:02       ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 06/22] ppc/ppc405: Start QOMification of the SoC Cédric Le Goater
2022-08-08 12:59   ` BALATON Zoltan
2022-08-08 15:20     ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU Cédric Le Goater
2022-08-08 13:17   ` BALATON Zoltan
2022-08-08 16:06     ` Cédric Le Goater
2022-08-08 17:05       ` BALATON Zoltan
2022-08-08 17:14         ` Peter Maydell
2022-08-08 17:25           ` BALATON Zoltan
2022-08-09 10:09             ` Cédric Le Goater
2022-08-08 10:27 ` Cédric Le Goater [this message]
2022-08-08 13:29   ` [PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model BALATON Zoltan
2022-08-08 15:35     ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 09/22] ppc/ppc405: QOM'ify CPC Cédric Le Goater
2022-08-08 14:12   ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 10/22] ppc/ppc405: QOM'ify GPT Cédric Le Goater
2022-08-08 14:25   ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 11/22] ppc/ppc405: QOM'ify OCM Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO Cédric Le Goater
2022-08-08 14:32   ` BALATON Zoltan
2022-08-08 14:50     ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 13/22] ppc/ppc405: QOM'ify DMA Cédric Le Goater
2022-08-08 14:35   ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 14/22] ppc/ppc405: QOM'ify EBC Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 15/22] ppc/ppc405: QOM'ify OPBA Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 16/22] ppc/ppc405: QOM'ify POB Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 17/22] ppc/ppc405: QOM'ify PLB Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 18/22] ppc/ppc405: QOM'ify MAL Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA Cédric Le Goater
2022-08-08 14:55   ` BALATON Zoltan
2022-08-08 15:58     ` Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 20/22] ppc/ppc405: Use an explicit PPCUIC object Cédric Le Goater
2022-08-08 14:58   ` BALATON Zoltan
2022-08-08 10:27 ` [PATCH v3 21/22] ppc/ppc405: Use an explicit I2C object Cédric Le Goater
2022-08-08 10:27 ` [PATCH v3 22/22] ppc/ppc4xx: Fix sdram trace events Cédric Le Goater
2022-08-08 12:16 ` [PATCH v3 00/22] ppc: QOM'ify 405 board BALATON Zoltan
2022-08-08 13:10   ` Cédric Le Goater
2022-08-08 14:08     ` BALATON Zoltan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220808102734.133084-9-clg@kaod.org \
    --to=clg@kaod.org \
    --cc=balaton@eik.bme.hu \
    --cc=danielhb413@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.