From: Chris Stillson <stillson@rivosinc.com>
To: linux-riscv@lists.infradead.org, jpalmer@dabbelt.com,
kvm-riscv@lists.infradead.org
Cc: Guo Ren <ren_guo@c-sky.com>, Guo Ren <guoren@linux.alibaba.com>,
Greentime Hu <greentime.hu@sifive.com>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH 01/17] riscv: Rename __switch_to_aux -> fpu
Date: Wed, 21 Sep 2022 12:46:13 -0700 [thread overview]
Message-ID: <20220921194629.1480202-2-stillson@rivosinc.com> (raw)
In-Reply-To: <20220921194629.1480202-1-stillson@rivosinc.com>
From: Guo Ren <ren_guo@c-sky.com>
The name of __switch_to_aux is not clear and rename it with the
determine function: __switch_to_fpu. Next we could add other regs'
switch.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/include/asm/switch_to.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 11463489fec6..df1aa589b7fd 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -46,7 +46,7 @@ static inline void fstate_restore(struct task_struct *task,
}
}
-static inline void __switch_to_aux(struct task_struct *prev,
+static inline void __switch_to_fpu(struct task_struct *prev,
struct task_struct *next)
{
struct pt_regs *regs;
@@ -65,7 +65,7 @@ static __always_inline bool has_fpu(void)
static __always_inline bool has_fpu(void) { return false; }
#define fstate_save(task, regs) do { } while (0)
#define fstate_restore(task, regs) do { } while (0)
-#define __switch_to_aux(__prev, __next) do { } while (0)
+#define __switch_to_fpu(__prev, __next) do { } while (0)
#endif
extern struct task_struct *__switch_to(struct task_struct *,
@@ -76,7 +76,7 @@ do { \
struct task_struct *__prev = (prev); \
struct task_struct *__next = (next); \
if (has_fpu()) \
- __switch_to_aux(__prev, __next); \
+ __switch_to_fpu(__prev, __next); \
((last) = __switch_to(__prev, __next)); \
} while (0)
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-21 21:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 19:46 [PATCH 00/17] Prctl to enable vector commands, previous vector patches rebased Chris Stillson
2022-09-21 19:46 ` Chris Stillson [this message]
2022-09-21 19:46 ` [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
2022-09-21 20:11 ` Conor Dooley
2022-09-21 21:33 ` Conor Dooley
2022-09-21 19:46 ` [PATCH 03/17] riscv: Add new csr defines related to vector extension Chris Stillson
2022-09-21 19:46 ` [PATCH 04/17] riscv: Add vector feature to compile Chris Stillson
2022-09-21 19:46 ` [PATCH 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson
2022-09-21 19:46 ` [PATCH 06/17] riscv: Reset vector register Chris Stillson
2022-09-21 19:46 ` [PATCH 07/17] riscv: Add vector struct and assembler definitions Chris Stillson
2022-09-21 19:46 ` [PATCH 08/17] riscv: Add task switch support for vector Chris Stillson
2022-09-21 19:46 ` [PATCH 09/17] riscv: Add ptrace vector support Chris Stillson
2022-09-21 19:46 ` [PATCH 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson
2022-09-21 19:46 ` [PATCH 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson
2022-09-21 19:46 ` [PATCH 12/17] riscv: Add support for kernel mode vector Chris Stillson
2022-09-21 19:46 ` [PATCH 13/17] riscv: Add vector extension XOR implementation Chris Stillson
2022-09-21 19:46 ` [PATCH 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson
2022-09-21 19:46 ` [PATCH 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson
2022-09-21 19:46 ` [PATCH 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson
2022-09-21 19:46 ` [PATCH 17/17] riscv: prctl to enable vector commands Chris Stillson
-- strict thread matches above, loose matches on Subject: below --
2022-09-21 16:45 [PATCH 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220921194629.1480202-2-stillson@rivosinc.com \
--to=stillson@rivosinc.com \
--cc=anup@brainfault.org \
--cc=greentime.hu@sifive.com \
--cc=guoren@linux.alibaba.com \
--cc=jpalmer@dabbelt.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@rivosinc.com \
--cc=ren_guo@c-sky.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.