From: Melody Olvera <quic_molvera@quicinc.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>
Cc: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Melody Olvera <quic_molvera@quicinc.com>
Subject: [PATCH 18/19] arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes
Date: Fri, 30 Sep 2022 20:06:55 -0700 [thread overview]
Message-ID: <20221001030656.29365-19-quic_molvera@quicinc.com> (raw)
In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com>
Add SPI devices to the QUP nodes for the QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 441 +++++++++++++++++++++++++
1 file changed, 441 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 40d7cc4c1f3d..930bb8c8ba5b 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -428,6 +428,132 @@ i2c6: i2c@998000 {
#size-cells = <0>;
status = "disabled";
};
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x984000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ dmas = <&gpi_dma0 0 1 1 64 0>,
+ <&gpi_dma0 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x988000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ dmas = <&gpi_dma0 0 2 1 64 0>,
+ <&gpi_dma0 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x98c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ dmas = <&gpi_dma0 0 3 1 64 0>,
+ <&gpi_dma0 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x990000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ dmas = <&gpi_dma0 0 4 1 64 0>,
+ <&gpi_dma0 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x994000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ dmas = <&gpi_dma0 0 5 1 64 0>,
+ <&gpi_dma0 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x998000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ dmas = <&gpi_dma0 0 6 1 64 0>,
+ <&gpi_dma0 1 6 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
};
qupv3_id_1: geniqup@ac0000 {
@@ -589,6 +715,153 @@ i2c15: i2c@a9c000 {
#size-cells = <0>;
status = "disabled";
};
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa84000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ dmas = <&gpi_dma1 0 1 1 64 0>,
+ <&gpi_dma1 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa88000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ dmas = <&gpi_dma1 0 2 1 64 0>,
+ <&gpi_dma1 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa8c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ dmas = <&gpi_dma1 0 3 1 64 0>,
+ <&gpi_dma1 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa90000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ dmas = <&gpi_dma1 0 4 1 64 0>,
+ <&gpi_dma1 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ dmas = <&gpi_dma1 0 5 1 64 0>,
+ <&gpi_dma1 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa98000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ dmas = <&gpi_dma1 0 6 1 64 0>,
+ <&gpi_dma1 1 6 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa9c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ dmas = <&gpi_dma1 0 7 1 64 0>,
+ <&gpi_dma1 1 7 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
};
@@ -746,6 +1019,174 @@ qup_i2c15_data_clk: qup-i2c15-data-clk {
bias-pulll-up;
};
+ qup_spi1_data_clk: qup-spi1-data-clk {
+ pins = "gpio10", "gpio11", "gpio12";
+ function = "qup0_se1_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio13";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk {
+ pins = "gpio12", "gpio13", "gpio10";
+ function = "qup0_se2_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk {
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup0_se3_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk {
+ pins = "gpio16", "gpio17", "gpio14";
+ function = "qup0_se4_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk {
+ pins = "gpio130", "gpio131", "gpio132";
+ function = "qup0_se5_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio133";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk {
+ pins = "gpio132", "gpio133", "gpio130";
+ function = "qup0_se6_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio131";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk {
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup1_se1_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio25";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk {
+ pins = "gpio24", "gpio25", "gpio22";
+ function = "qup1_se2_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk {
+ pins = "gpio26", "gpio27", "gpio28";
+ function = "qup1_se3_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio29";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk {
+ pins = "gpio28", "gpio29", "gpio26";
+ function = "qup1_se4_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk {
+ pins = "gpio30", "gpio31", "gpio32";
+ function = "qup1_se5_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio33";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk {
+ pins = "gpio34", "gpio35", "gpio36";
+ function = "qup1_se6_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio37", "gpio38";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio40", "gpio41", "gpio30";
+ function = "qup1_se7_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
};
pdc: interrupt-controller@b220000 {
--
2.37.3
next prev parent reply other threads:[~2022-10-01 3:09 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
2022-10-01 7:22 ` Dmitry Baryshkov
2022-10-11 18:21 ` Melody Olvera
2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-11 18:22 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
2022-10-01 7:28 ` Dmitry Baryshkov
2022-10-11 18:29 ` Melody Olvera
2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-11 18:31 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Melody Olvera
2022-10-01 7:26 ` Dmitry Baryshkov
2022-10-11 18:40 ` Melody Olvera
2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-11 18:48 ` Melody Olvera
2022-10-11 18:57 ` Krzysztof Kozlowski
2022-10-11 19:05 ` Melody Olvera
2022-10-11 19:19 ` Krzysztof Kozlowski
2022-10-11 20:01 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes Melody Olvera
2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 05/19] arm64: dts: qcom: qru1000: " Melody Olvera
2022-10-01 3:06 ` [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes Melody Olvera
2022-10-01 7:23 ` Dmitry Baryshkov
2022-10-01 3:06 ` [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes Melody Olvera
2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-11 21:08 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 08/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-11 21:08 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes Melody Olvera
2022-10-01 9:16 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 10/19] arm64: dts: qcom: qdru1000: Add rpmhpd node Melody Olvera
2022-10-01 3:06 ` [PATCH 11/19] arm64: dts: qcom: qdru1000: Add spmi node Melody Olvera
2022-10-01 3:06 ` [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file Melody Olvera
2022-10-01 9:16 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 13/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
2022-10-01 3:06 ` [PATCH 14/19] arm64: dts: qcom: qdru1000: Add cpufreq support Melody Olvera
2022-10-01 3:06 ` [PATCH 15/19] arm64: dts: qcom: qdru1000: Add additional QUP nodes Melody Olvera
2022-10-01 3:06 ` [PATCH 16/19] arm64: dts: qcom: qdru1000: Add gpi_dma nodes Melody Olvera
2022-10-01 3:06 ` [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP Melody Olvera
2022-10-01 7:30 ` Dmitry Baryshkov
2022-10-01 3:06 ` Melody Olvera [this message]
2022-10-01 3:06 ` [PATCH 19/19] arm64: dts: qcom: qdru1000: Add additional UART instances Melody Olvera
2022-10-01 7:32 ` [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Dmitry Baryshkov
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