[PATCH 4/5] spi: tegra210-quad: combined seq for 4READ

From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
To: <broonie@kernel.org>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <linux-spi@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>
Cc: <skomatineni@nvidia.com>, <ldewangan@nvidia.com>,
	<linux-kernel@vger.kernel.org>,
	Krishna Yarlagadda <kyarlagadda@nvidia.com>
Subject: [PATCH 4/5] spi: tegra210-quad: combined seq for 4READ
Date: Sat, 1 Oct 2022 17:51:47 +0530	[thread overview]
Message-ID: <20221001122148.9158-4-kyarlagadda@nvidia.com> (raw)
In-Reply-To: <20221001122148.9158-1-kyarlagadda@nvidia.com>

X2 and X4 reads require dummy cycles. Use hardware dummy clock cycles
programming to use combined sequence for X2, X4 transfers as well.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 drivers/spi/spi-tegra210-quad.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index be11daafb7d4..99811509dafa 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -159,7 +159,8 @@
 #define DEFAULT_QSPI_DMA_BUF_LEN		(64 * 1024)
 #define CMD_TRANSFER				0
 #define ADDR_TRANSFER				1
-#define DATA_TRANSFER				2
+#define DUMMY_TRANSFER				2
+#define DATA_TRANSFER				3
 
 struct tegra_qspi_soc_data {
 	bool has_dma;
@@ -1072,7 +1073,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
 							     xfer->len);
 			address_value = *((const u32 *)(xfer->tx_buf));
 			break;
+		case DUMMY_TRANSFER:
 		case DATA_TRANSFER:
+			if (xfer->dummy_data) {
+				tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits;
+				break;
+			}
 			/* Program Command, Address value in register */
 			tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
 			tegra_qspi_writel(tqspi, address_value,
@@ -1277,7 +1283,9 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi,
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 		transfer_count++;
 	}
-	if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3)
+	if (!tqspi->soc_data->cmb_xfer_capable)
+		return false;
+	if (transfer_count > 4 || transfer_count < 3)
 		return false;
 	xfer = list_first_entry(&msg->transfers, typeof(*xfer),
 				transfer_list);
@@ -1287,7 +1295,15 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi,
 	if (xfer->len > 4 || xfer->len < 3)
 		return false;
 	xfer = list_next_entry(xfer, transfer_list);
-	if (!tqspi->soc_data->has_dma || xfer->len > (QSPI_FIFO_DEPTH << 2))
+	if (transfer_count == 4) {
+		if (xfer->dummy_data != 1)
+			return false;
+		if ((xfer->len * 8 / xfer->tx_nbits) >
+		   QSPI_DUMMY_CYCLES_MAX)
+			return false;
+		xfer = list_next_entry(xfer, transfer_list);
+	}
+	if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2))
 		return false;
 
 	return true;
-- 
2.17.1

