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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v7 05/18] accel/tcg: Drop addr member from SavedIOTLB
Date: Tue,  4 Oct 2022 07:10:38 -0700	[thread overview]
Message-ID: <20221004141051.110653-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221004141051.110653-1-richard.henderson@linaro.org>

This field is only written, not read; remove it.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h | 1 -
 accel/tcg/cputlb.c    | 7 +++----
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1a7e1a9380..009dc0d336 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -225,7 +225,6 @@ struct CPUWatchpoint {
  * the memory regions get moved around  by io_writex.
  */
 typedef struct SavedIOTLB {
-    hwaddr addr;
     MemoryRegionSection *section;
     hwaddr mr_offset;
 } SavedIOTLB;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index aa22f578cb..d06ff44ce9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1372,12 +1372,11 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
  * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
  * because of the side effect of io_writex changing memory layout.
  */
-static void save_iotlb_data(CPUState *cs, hwaddr addr,
-                            MemoryRegionSection *section, hwaddr mr_offset)
+static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section,
+                            hwaddr mr_offset)
 {
 #ifdef CONFIG_PLUGIN
     SavedIOTLB *saved = &cs->saved_iotlb;
-    saved->addr = addr;
     saved->section = section;
     saved->mr_offset = mr_offset;
 #endif
@@ -1406,7 +1405,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
      * The memory_region_dispatch may trigger a flush/resize
      * so for plugins we save the iotlb_data just in case.
      */
-    save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
+    save_iotlb_data(cpu, section, mr_offset);
 
     if (!qemu_mutex_iothread_locked()) {
         qemu_mutex_lock_iothread();
-- 
2.34.1



  parent reply	other threads:[~2022-10-04 15:05 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-04 14:10 [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Richard Henderson
2022-10-04 14:10 ` [PATCH v7 01/18] cpu: cache CPUClass in CPUState for hot code paths Richard Henderson
2022-10-04 14:10 ` [PATCH v7 02/18] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs Richard Henderson
2022-10-04 14:10 ` [PATCH v7 03/18] cputlb: used cached CPUClass in our hot-paths Richard Henderson
2022-10-04 14:10 ` [PATCH v7 04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull Richard Henderson
2022-10-04 14:10 ` Richard Henderson [this message]
2022-10-04 14:10 ` [PATCH v7 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal Richard Henderson
2022-10-04 14:10 ` [PATCH v7 07/18] accel/tcg: Introduce probe_access_full Richard Henderson
2022-10-04 14:10 ` [PATCH v7 08/18] accel/tcg: Introduce tlb_set_page_full Richard Henderson
2022-10-11  5:01   ` Alistair Francis
2022-10-11 15:08     ` Richard Henderson
2022-10-04 14:10 ` [PATCH v7 09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA Richard Henderson
2022-10-04 14:10 ` [PATCH v7 10/18] accel/tcg: Remove PageDesc code_bitmap Richard Henderson
2022-10-04 14:10 ` [PATCH v7 11/18] accel/tcg: Use bool for page_find_alloc Richard Henderson
2022-10-04 14:10 ` [PATCH v7 12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Richard Henderson
2022-10-04 14:10 ` [PATCH v7 13/18] accel/tcg: Do not align tb->page_addr[0] Richard Henderson
2022-10-04 15:34   ` Alex Bennée
2022-10-04 14:10 ` [PATCH v7 14/18] accel/tcg: Inline tb_flush_jmp_cache Richard Henderson
2022-10-04 14:10 ` [PATCH v7 15/18] include/hw/core: Create struct CPUJumpCache Richard Henderson
2022-10-04 14:10 ` [PATCH v7 16/18] hw/core: Add CPUClass.get_pc Richard Henderson
2022-10-04 14:10 ` [PATCH v7 17/18] accel/tcg: Introduce tb_pc and log_pc Richard Henderson
2022-10-04 15:39   ` Alex Bennée
2022-10-04 14:10 ` [PATCH v7 18/18] accel/tcg: Introduce TARGET_TB_PCREL Richard Henderson
2022-10-04 15:48   ` Alex Bennée

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