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From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Huai-Cheng Kuo <hchkuo@avery-design.com.tw>,
	Chris Browy <cbrowy@avery-design.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Ben Widawsky <ben.widawsky@intel.com>
Subject: [PULL v2 28/82] hw/cxl/cdat: CXL CDAT Data Object Exchange implementation
Date: Wed, 2 Nov 2022 12:09:37 -0400	[thread overview]
Message-ID: <20221102160336.616599-29-mst@redhat.com> (raw)
In-Reply-To: <20221102160336.616599-1-mst@redhat.com>

From: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>

The Data Object Exchange implementation of CXL Coherent Device Attribute
Table (CDAT). This implementation is referring to "Coherent Device
Attribute Table Specification, Rev. 1.03, July. 2022" and "Compute
Express Link Specification, Rev. 3.0, July. 2022"

This patch adds core support that will be shared by both
end-points and switch port emulation.

Signed-off-by: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/cxl/cxl_cdat.h      | 165 ++++++++++++++++++++++++
 include/hw/cxl/cxl_component.h |   7 ++
 include/hw/cxl/cxl_device.h    |   3 +
 include/hw/cxl/cxl_pci.h       |   1 +
 hw/cxl/cxl-cdat.c              | 224 +++++++++++++++++++++++++++++++++
 hw/cxl/meson.build             |   1 +
 6 files changed, 401 insertions(+)
 create mode 100644 include/hw/cxl/cxl_cdat.h
 create mode 100644 hw/cxl/cxl-cdat.c

diff --git a/include/hw/cxl/cxl_cdat.h b/include/hw/cxl/cxl_cdat.h
new file mode 100644
index 0000000000..52c232e912
--- /dev/null
+++ b/include/hw/cxl/cxl_cdat.h
@@ -0,0 +1,165 @@
+/*
+ * CXL CDAT Structure
+ *
+ * Copyright (C) 2021 Avery Design Systems, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef CXL_CDAT_H
+#define CXL_CDAT_H
+
+#include "hw/cxl/cxl_pci.h"
+
+/*
+ * Reference:
+ *   Coherent Device Attribute Table (CDAT) Specification, Rev. 1.03, July. 2022
+ *   Compute Express Link (CXL) Specification, Rev. 3.0, Aug. 2022
+ */
+/* Table Access DOE - CXL r3.0 8.1.11 */
+#define CXL_DOE_TABLE_ACCESS      2
+#define CXL_DOE_PROTOCOL_CDAT     ((CXL_DOE_TABLE_ACCESS << 16) | CXL_VENDOR_ID)
+
+/* Read Entry - CXL r3.0 8.1.11.1 */
+#define CXL_DOE_TAB_TYPE_CDAT 0
+#define CXL_DOE_TAB_ENT_MAX 0xFFFF
+
+/* Read Entry Request - CXL r3.0 8.1.11.1 Table 8-13 */
+#define CXL_DOE_TAB_REQ 0
+typedef struct CDATReq {
+    DOEHeader header;
+    uint8_t req_code;
+    uint8_t table_type;
+    uint16_t entry_handle;
+} QEMU_PACKED CDATReq;
+
+/* Read Entry Response - CXL r3.0 8.1.11.1 Table 8-14 */
+#define CXL_DOE_TAB_RSP 0
+typedef struct CDATRsp {
+    DOEHeader header;
+    uint8_t rsp_code;
+    uint8_t table_type;
+    uint16_t entry_handle;
+} QEMU_PACKED CDATRsp;
+
+/* CDAT Table Format - CDAT Table 1 */
+#define CXL_CDAT_REV 2
+typedef struct CDATTableHeader {
+    uint32_t length;
+    uint8_t revision;
+    uint8_t checksum;
+    uint8_t reserved[6];
+    uint32_t sequence;
+} QEMU_PACKED CDATTableHeader;
+
+/* CDAT Structure Types - CDAT Table 2 */
+typedef enum {
+    CDAT_TYPE_DSMAS = 0,
+    CDAT_TYPE_DSLBIS = 1,
+    CDAT_TYPE_DSMSCIS = 2,
+    CDAT_TYPE_DSIS = 3,
+    CDAT_TYPE_DSEMTS = 4,
+    CDAT_TYPE_SSLBIS = 5,
+} CDATType;
+
+typedef struct CDATSubHeader {
+    uint8_t type;
+    uint8_t reserved;
+    uint16_t length;
+} CDATSubHeader;
+
+/* Device Scoped Memory Affinity Structure - CDAT Table 3 */
+typedef struct CDATDsmas {
+    CDATSubHeader header;
+    uint8_t DSMADhandle;
+    uint8_t flags;
+#define CDAT_DSMAS_FLAG_NV              (1 << 2)
+#define CDAT_DSMAS_FLAG_SHAREABLE       (1 << 3)
+#define CDAT_DSMAS_FLAG_HW_COHERENT     (1 << 4)
+#define CDAT_DSMAS_FLAG_DYNAMIC_CAP     (1 << 5)
+    uint16_t reserved;
+    uint64_t DPA_base;
+    uint64_t DPA_length;
+} QEMU_PACKED CDATDsmas;
+
+/* Device Scoped Latency and Bandwidth Information Structure - CDAT Table 5 */
+typedef struct CDATDslbis {
+    CDATSubHeader header;
+    uint8_t handle;
+    /* Definitions of these fields refer directly to HMAT fields */
+    uint8_t flags;
+    uint8_t data_type;
+    uint8_t reserved;
+    uint64_t entry_base_unit;
+    uint16_t entry[3];
+    uint16_t reserved2;
+} QEMU_PACKED CDATDslbis;
+
+/* Device Scoped Memory Side Cache Information Structure - CDAT Table 6 */
+typedef struct CDATDsmscis {
+    CDATSubHeader header;
+    uint8_t DSMAS_handle;
+    uint8_t reserved[3];
+    uint64_t memory_side_cache_size;
+    uint32_t cache_attributes;
+} QEMU_PACKED CDATDsmscis;
+
+/* Device Scoped Initiator Structure - CDAT Table 7 */
+typedef struct CDATDsis {
+    CDATSubHeader header;
+    uint8_t flags;
+    uint8_t handle;
+    uint16_t reserved;
+} QEMU_PACKED CDATDsis;
+
+/* Device Scoped EFI Memory Type Structure - CDAT Table 8 */
+typedef struct CDATDsemts {
+    CDATSubHeader header;
+    uint8_t DSMAS_handle;
+    uint8_t EFI_memory_type_attr;
+    uint16_t reserved;
+    uint64_t DPA_offset;
+    uint64_t DPA_length;
+} QEMU_PACKED CDATDsemts;
+
+/* Switch Scoped Latency and Bandwidth Information Structure - CDAT Table 9 */
+typedef struct CDATSslbisHeader {
+    CDATSubHeader header;
+    uint8_t data_type;
+    uint8_t reserved[3];
+    uint64_t entry_base_unit;
+} QEMU_PACKED CDATSslbisHeader;
+
+/* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */
+typedef struct CDATSslbe {
+    uint16_t port_x_id;
+    uint16_t port_y_id;
+    uint16_t latency_bandwidth;
+    uint16_t reserved;
+} QEMU_PACKED CDATSslbe;
+
+typedef struct CDATSslbis {
+    CDATSslbisHeader sslbis_header;
+    CDATSslbe sslbe[];
+} QEMU_PACKED CDATSslbis;
+
+typedef struct CDATEntry {
+    void *base;
+    uint32_t length;
+} CDATEntry;
+
+typedef struct CDATObject {
+    CDATEntry *entry;
+    int entry_len;
+
+    int (*build_cdat_table)(CDATSubHeader ***cdat_table, void *priv);
+    void (*free_cdat_table)(CDATSubHeader **cdat_table, int num, void *priv);
+    bool to_update;
+    void *private;
+    char *filename;
+    uint8_t *buf;
+    struct CDATSubHeader **built_buf;
+    int built_buf_len;
+} CDATObject;
+#endif /* CXL_CDAT_H */
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 94ec2f07d7..34075cfb72 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -19,6 +19,7 @@
 #include "qemu/range.h"
 #include "qemu/typedefs.h"
 #include "hw/register.h"
+#include "qapi/error.h"
 
 enum reg_type {
     CXL2_DEVICE,
@@ -184,6 +185,8 @@ typedef struct cxl_component {
             struct PCIDevice *pdev;
         };
     };
+
+    CDATObject cdat;
 } CXLComponentState;
 
 void cxl_component_register_block_init(Object *obj,
@@ -220,4 +223,8 @@ static inline hwaddr cxl_decode_ig(int ig)
 
 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb);
 
+void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp);
+void cxl_doe_cdat_release(CXLComponentState *cxl_cstate);
+void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp);
+
 #endif
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index e4d221cdb3..449b0edfe9 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -243,6 +243,9 @@ struct CXLType3Dev {
     AddressSpace hostmem_as;
     CXLComponentState cxl_cstate;
     CXLDeviceState cxl_dstate;
+
+    /* DOE */
+    DOECap doe_cdat;
 };
 
 #define TYPE_CXL_TYPE3 "cxl-type3"
diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h
index 01cf002096..3cb79eca1e 100644
--- a/include/hw/cxl/cxl_pci.h
+++ b/include/hw/cxl/cxl_pci.h
@@ -13,6 +13,7 @@
 #include "qemu/compiler.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pcie.h"
+#include "hw/cxl/cxl_cdat.h"
 
 #define CXL_VENDOR_ID 0x1e98
 
diff --git a/hw/cxl/cxl-cdat.c b/hw/cxl/cxl-cdat.c
new file mode 100644
index 0000000000..3653aa56f0
--- /dev/null
+++ b/hw/cxl/cxl-cdat.c
@@ -0,0 +1,224 @@
+/*
+ * CXL CDAT Structure
+ *
+ * Copyright (C) 2021 Avery Design Systems, Inc.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci/pci.h"
+#include "hw/cxl/cxl.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+
+static void cdat_len_check(CDATSubHeader *hdr, Error **errp)
+{
+    assert(hdr->length);
+    assert(hdr->reserved == 0);
+
+    switch (hdr->type) {
+    case CDAT_TYPE_DSMAS:
+        assert(hdr->length == sizeof(CDATDsmas));
+        break;
+    case CDAT_TYPE_DSLBIS:
+        assert(hdr->length == sizeof(CDATDslbis));
+        break;
+    case CDAT_TYPE_DSMSCIS:
+        assert(hdr->length == sizeof(CDATDsmscis));
+        break;
+    case CDAT_TYPE_DSIS:
+        assert(hdr->length == sizeof(CDATDsis));
+        break;
+    case CDAT_TYPE_DSEMTS:
+        assert(hdr->length == sizeof(CDATDsemts));
+        break;
+    case CDAT_TYPE_SSLBIS:
+        assert(hdr->length >= sizeof(CDATSslbisHeader));
+        assert((hdr->length - sizeof(CDATSslbisHeader)) %
+               sizeof(CDATSslbe) == 0);
+        break;
+    default:
+        error_setg(errp, "Type %d is reserved", hdr->type);
+    }
+}
+
+static void ct3_build_cdat(CDATObject *cdat, Error **errp)
+{
+    g_autofree CDATTableHeader *cdat_header = NULL;
+    g_autofree CDATEntry *cdat_st = NULL;
+    uint8_t sum = 0;
+    int ent, i;
+
+    /* Use default table if fopen == NULL */
+    assert(cdat->build_cdat_table);
+
+    cdat_header = g_malloc0(sizeof(*cdat_header));
+    if (!cdat_header) {
+        error_setg(errp, "Failed to allocate CDAT header");
+        return;
+    }
+
+    cdat->built_buf_len = cdat->build_cdat_table(&cdat->built_buf, cdat->private);
+
+    if (!cdat->built_buf_len) {
+        /* Build later as not all data available yet */
+        cdat->to_update = true;
+        return;
+    }
+    cdat->to_update = false;
+
+    cdat_st = g_malloc0(sizeof(*cdat_st) * (cdat->built_buf_len + 1));
+    if (!cdat_st) {
+        error_setg(errp, "Failed to allocate CDAT entry array");
+        return;
+    }
+
+    /* Entry 0 for CDAT header, starts with Entry 1 */
+    for (ent = 1; ent < cdat->built_buf_len + 1; ent++) {
+        CDATSubHeader *hdr = cdat->built_buf[ent - 1];
+        uint8_t *buf = (uint8_t *)cdat->built_buf[ent - 1];
+
+        cdat_st[ent].base = hdr;
+        cdat_st[ent].length = hdr->length;
+
+        cdat_header->length += hdr->length;
+        for (i = 0; i < hdr->length; i++) {
+            sum += buf[i];
+        }
+    }
+
+    /* CDAT header */
+    cdat_header->revision = CXL_CDAT_REV;
+    /* For now, no runtime updates */
+    cdat_header->sequence = 0;
+    cdat_header->length += sizeof(CDATTableHeader);
+    sum += cdat_header->revision + cdat_header->sequence +
+        cdat_header->length;
+    /* Sum of all bytes including checksum must be 0 */
+    cdat_header->checksum = ~sum + 1;
+
+    cdat_st[0].base = g_steal_pointer(&cdat_header);
+    cdat_st[0].length = sizeof(*cdat_header);
+    cdat->entry_len = 1 + cdat->built_buf_len;
+    cdat->entry = g_steal_pointer(&cdat_st);
+}
+
+static void ct3_load_cdat(CDATObject *cdat, Error **errp)
+{
+    g_autofree CDATEntry *cdat_st = NULL;
+    uint8_t sum = 0;
+    int num_ent;
+    int i = 0, ent = 1, file_size = 0;
+    CDATSubHeader *hdr;
+    FILE *fp = NULL;
+
+    /* Read CDAT file and create its cache */
+    fp = fopen(cdat->filename, "r");
+    if (!fp) {
+        error_setg(errp, "CDAT: Unable to open file");
+        return;
+    }
+
+    fseek(fp, 0, SEEK_END);
+    file_size = ftell(fp);
+    fseek(fp, 0, SEEK_SET);
+    cdat->buf = g_malloc0(file_size);
+
+    if (fread(cdat->buf, file_size, 1, fp) == 0) {
+        error_setg(errp, "CDAT: File read failed");
+        return;
+    }
+
+    fclose(fp);
+
+    if (file_size < sizeof(CDATTableHeader)) {
+        error_setg(errp, "CDAT: File too short");
+        return;
+    }
+    i = sizeof(CDATTableHeader);
+    num_ent = 1;
+    while (i < file_size) {
+        hdr = (CDATSubHeader *)(cdat->buf + i);
+        cdat_len_check(hdr, errp);
+        i += hdr->length;
+        num_ent++;
+    }
+    if (i != file_size) {
+        error_setg(errp, "CDAT: File length missmatch");
+        return;
+    }
+
+    cdat_st = g_malloc0(sizeof(*cdat_st) * num_ent);
+    if (!cdat_st) {
+        error_setg(errp, "CDAT: Failed to allocate entry array");
+        return;
+    }
+
+    /* Set CDAT header, Entry = 0 */
+    cdat_st[0].base = cdat->buf;
+    cdat_st[0].length = sizeof(CDATTableHeader);
+    i = 0;
+
+    while (i < cdat_st[0].length) {
+        sum += cdat->buf[i++];
+    }
+
+    /* Read CDAT structures */
+    while (i < file_size) {
+        hdr = (CDATSubHeader *)(cdat->buf + i);
+        cdat_len_check(hdr, errp);
+
+        cdat_st[ent].base = hdr;
+        cdat_st[ent].length = hdr->length;
+
+        while (cdat->buf + i <
+               (uint8_t *)cdat_st[ent].base + cdat_st[ent].length) {
+            assert(i < file_size);
+            sum += cdat->buf[i++];
+        }
+
+        ent++;
+    }
+
+    if (sum != 0) {
+        warn_report("CDAT: Found checksum mismatch in %s", cdat->filename);
+    }
+    cdat->entry_len = num_ent;
+    cdat->entry = g_steal_pointer(&cdat_st);
+}
+
+void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp)
+{
+    CDATObject *cdat = &cxl_cstate->cdat;
+
+    if (cdat->filename) {
+        ct3_load_cdat(cdat, errp);
+    } else {
+        ct3_build_cdat(cdat, errp);
+    }
+}
+
+void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp)
+{
+    CDATObject *cdat = &cxl_cstate->cdat;
+
+    if (cdat->to_update) {
+        ct3_build_cdat(cdat, errp);
+    }
+}
+
+void cxl_doe_cdat_release(CXLComponentState *cxl_cstate)
+{
+    CDATObject *cdat = &cxl_cstate->cdat;
+
+    free(cdat->entry);
+    if (cdat->built_buf) {
+        cdat->free_cdat_table(cdat->built_buf, cdat->built_buf_len,
+                              cdat->private);
+    }
+    if (cdat->buf) {
+        free(cdat->buf);
+    }
+}
diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build
index f117b99949..cfa95ffd40 100644
--- a/hw/cxl/meson.build
+++ b/hw/cxl/meson.build
@@ -4,6 +4,7 @@ softmmu_ss.add(when: 'CONFIG_CXL',
                    'cxl-device-utils.c',
                    'cxl-mailbox-utils.c',
                    'cxl-host.c',
+                   'cxl-cdat.c',
                ),
                if_false: files(
                    'cxl-host-stubs.c',
-- 
MST



  parent reply	other threads:[~2022-11-02 16:21 UTC|newest]

Thread overview: 113+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-02 16:02 [PULL v2 00/82] pci,pc,virtio: features, tests, fixes, cleanups Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 01/82] hw/i386/e820: remove legacy reserved entries for e820 Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 02/82] tests/acpi: allow SSDT changes Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 03/82] acpi/ssdt: Fix aml_or() and aml_and() in if clause Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 04/82] acpi/nvdimm: define macro for NVDIMM Device _DSM Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 05/82] acpi/nvdimm: Implement ACPI NVDIMM Label Methods Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 06/82] test/acpi/bios-tables-test: SSDT: update golden master binaries Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 07/82] virtio-crypto: Support asynchronous mode Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 08/82] crypto: Support DER encodings Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 09/82] crypto: Support export akcipher to pkcs8 Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 10/82] cryptodev: Add a lkcf-backend for cryptodev Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 11/82] acpi/tests/avocado/bits: initial commit of test scripts that are run by biosbits Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 12/82] acpi/tests/avocado/bits: disable acpi PSS tests that are failing in biosbits Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 13/82] acpi/tests/avocado/bits: add biosbits config file for running bios tests Michael S. Tsirkin
2022-11-02 16:08 ` [PULL v2 14/82] acpi/tests/avocado/bits: add acpi and smbios avocado tests that uses biosbits Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 15/82] acpi/tests/avocado/bits/doc: add a doc file to describe the acpi bits test Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 16/82] MAINTAINERS: add myself as the maintainer for acpi biosbits avocado tests Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 17/82] hw/smbios: add core_count2 to smbios table type 4 Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 18/82] bios-tables-test: teach test to use smbios 3.0 tables Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 19/82] tests/acpi: allow changes for core_count2 test Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 20/82] bios-tables-test: add test for number of cores > 255 Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 21/82] tests/acpi: update tables for new core count test Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 22/82] tests/acpi: virt: allow acpi MADT and FADT changes Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 23/82] acpi: fadt: support revision 6.0 of the ACPI specification Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 24/82] acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata A Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 25/82] tests/acpi: virt: update ACPI MADT and FADT binaries Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 26/82] hw/pci: PCIe Data Object Exchange emulation Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 27/82] hw/mem/cxl-type3: Add MSIX support Michael S. Tsirkin
2022-11-02 16:09 ` Michael S. Tsirkin [this message]
2022-11-02 16:09 ` [PULL v2 29/82] hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 30/82] hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 31/82] vhost: Change the sequence of device start Michael S. Tsirkin
2022-11-05 16:35   ` Bernhard Beschow
2022-11-05 16:43     ` Michael S. Tsirkin
2022-11-06 18:00       ` Christian A. Ehrhardt
2022-11-07 13:30         ` Michael S. Tsirkin
2022-11-07 17:31           ` Christian A. Ehrhardt
2022-11-07 17:54             ` Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 32/82] vhost-user: Support vhost_dev_start Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 33/82] hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 34/82] virtio: re-order vm_running and use_started checks Michael S. Tsirkin
2022-11-02 16:09 ` [PULL v2 35/82] virtio: introduce __virtio_queue_reset() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 36/82] virtio: introduce virtio_queue_reset() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 37/82] virtio: introduce virtio_queue_enable() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 38/82] virtio: core: vq reset feature negotation support Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 39/82] virtio-pci: support queue reset Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 40/82] virtio-pci: support queue enable Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 41/82] vhost: expose vhost_virtqueue_start() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 42/82] vhost: expose vhost_virtqueue_stop() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 43/82] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_reset() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 44/82] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_restart() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 45/82] virtio-net: introduce flush_or_purge_queued_packets() Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 46/82] virtio-net: support queue reset Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 47/82] virtio-net: support queue_enable Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 48/82] vhost: vhost-kernel: enable vq reset feature Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 49/82] virtio-net: " Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 50/82] virtio-rng-pci: Allow setting nvectors, so we can use MSI-X Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 51/82] vhost-user: Fix out of order vring host notification handling Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 52/82] acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 53/82] tests: acpi: whitelist DSDT before generating PCI-ISA bridge AML automatically Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 54/82] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 55/82] tests: acpi: update expected DSDT after ISA bridge is moved directly under PCI host bridge Michael S. Tsirkin
2022-11-02 16:10 ` [PULL v2 56/82] tests: acpi: whitelist DSDT before generating ICH9_SMB AML automatically Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 57/82] acpi: add get_dev_aml_func() helper Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 58/82] acpi: enumerate SMB bridge automatically along with other PCI devices Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 59/82] tests: acpi: update expected blobs Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 60/82] tests: acpi: pc/q35 whitelist DSDT before \_GPE cleanup Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 61/82] acpi: pc/35: sanitize _GPE declaration order Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 62/82] tests: acpi: update expected blobs Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 63/82] hw/acpi/erst.c: Fix memory handling issues Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 64/82] MAINTAINERS: Add qapi/virtio.json to section "virtio" Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 65/82] msix: Assert that specified vector is in range Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 66/82] hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 67/82] hw/i386/acpi-build: Remove unused struct Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 68/82] hw/i386/acpi-build: Resolve redundant attribute Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 69/82] hw/i386/acpi-build: Resolve north rather than south bridges Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 70/82] hmat acpi: Don't require initiator value in -numa Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 71/82] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 72/82] tests: acpi: q35: add test for hmat nodes without initiators Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 73/82] tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT: Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 74/82] tests: Add HMAT AArch64/virt empty table files Michael S. Tsirkin
2022-11-02 16:11 ` [PULL v2 75/82] hw/arm/virt: Enable HMAT on arm virt machine Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 76/82] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 77/82] tests: virt: Update expected *.acpihmatvirt tables Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 78/82] vfio: move implement of vfio_get_xlat_addr() to memory.c Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 79/82] intel-iommu: don't warn guest errors when getting rid2pasid entry Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 80/82] intel-iommu: drop VTDBus Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 81/82] intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function Michael S. Tsirkin
2022-11-02 16:12 ` [PULL v2 82/82] intel-iommu: PASID support Michael S. Tsirkin
2022-11-02 19:47 ` [PULL v2 00/82] pci,pc,virtio: features, tests, fixes, cleanups Stefan Hajnoczi
2022-11-03 12:13   ` Michael S. Tsirkin
2022-11-03 13:29     ` Stefan Hajnoczi
2022-11-03 14:54       ` Michael S. Tsirkin
2022-11-03 21:59       ` Michael S. Tsirkin
2022-11-03 13:31     ` Philippe Mathieu-Daudé
2022-11-03 15:42       ` Ani Sinha
2022-11-03 15:49         ` Stefan Hajnoczi
2022-11-03 15:58           ` Michael S. Tsirkin
2022-11-03 16:27             ` Stefan Hajnoczi
2022-11-03 15:59           ` Daniel P. Berrangé
2022-11-03 16:25             ` Stefan Hajnoczi
2022-11-03 16:38               ` Daniel P. Berrangé
2022-11-03 16:47                 ` Peter Maydell
2022-11-03 16:49                   ` Daniel P. Berrangé
2022-11-03 17:05                     ` Stefan Hajnoczi
2022-11-03 16:47                 ` Daniel P. Berrangé
2022-11-03 16:47         ` Ani Sinha
2022-11-03 16:48           ` Ani Sinha
2022-11-03 16:56             ` Ani Sinha
2022-11-03 17:41               ` Daniel P. Berrangé
2022-11-03 17:44                 ` Ani Sinha
2022-11-03 20:32                   ` Michael S. Tsirkin
2022-11-04  3:07                     ` Ani Sinha

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