From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhao Liu <zhao1.liu@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>
Subject: [PATCH 13/18] hw/i386/pc: Support smp.clusters for x86 PC machine
Date: Thu, 2 Feb 2023 17:49:24 +0800 [thread overview]
Message-ID: <20230202094929.343799-14-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com>
From: Zhuocheng Ding <zhuocheng.ding@intel.com>
As module-level topology support is added to X86CPU, now we can enable
the support for the cluster parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,clusters=*,cores=*,threads=*.
Additionally, add the 5-level topology example in description of "-smp".
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
hw/i386/pc.c | 1 +
qemu-options.hx | 10 +++++-----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6e592bd969aa..c329df56ebd2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1929,6 +1929,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
+ mc->smp_props.clusters_supported = true;
mc->default_ram_id = "pc.ram";
object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
diff --git a/qemu-options.hx b/qemu-options.hx
index d59d19704bc5..3700e1aa97ea 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -312,14 +312,14 @@ SRST
-smp 8,sockets=2,cores=2,threads=2,maxcpus=8
The following sub-option defines a CPU topology hierarchy (2 sockets
- totally on the machine, 2 dies per socket, 2 cores per die, 2 threads
- per core) for PC machines which support sockets/dies/cores/threads.
- Some members of the option can be omitted but their values will be
- automatically computed:
+ totally on the machine, 2 dies per socket, 2 clusters per die, 2 cores per
+ cluster, 2 threads per core) for PC machines which support sockets/dies
+ /clusters/cores/threads. Some members of the option can be omitted but
+ their values will be automatically computed:
::
- -smp 16,sockets=2,dies=2,cores=2,threads=2,maxcpus=16
+ -smp 32,sockets=2,dies=2,clusters=2,cores=2,threads=2,maxcpus=32
The following sub-option defines a CPU topology hierarchy (2 sockets
totally on the machine, 2 clusters per socket, 2 cores per cluster,
--
2.34.1
next prev parent reply other threads:[~2023-02-02 9:46 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-02 9:49 [PATCH 00/18] Support smp.clusters for x86 Zhao Liu
2023-02-02 9:49 ` [PATCH 01/18] machine: Fix comment of machine_parse_smp_config() Zhao Liu
2023-02-02 9:49 ` [PATCH 02/18] tests: Rename test-x86-cpuid.c to test-x86-apicid.c Zhao Liu
2023-02-02 9:49 ` [PATCH 03/18] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-02-02 9:49 ` [PATCH 04/18] i386/cpu: Fix number of addressable IDs in CPUID.04H Zhao Liu
2023-02-02 9:49 ` [PATCH 05/18] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-02-02 9:49 ` [PATCH 06/18] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-02-02 9:49 ` [PATCH 07/18] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-02-02 9:49 ` [PATCH 08/18] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-02-02 9:49 ` [PATCH 09/18] i386: Fix comment style in topology.h Zhao Liu
2023-02-02 9:49 ` [PATCH 10/18] i386: Update APIC ID parsing rule to support module level Zhao Liu
2023-02-02 9:49 ` [PATCH 11/18] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-02-02 9:49 ` [PATCH 12/18] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-02-02 9:49 ` Zhao Liu [this message]
2023-02-02 9:49 ` [PATCH 14/18] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-02-02 9:49 ` [PATCH 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14] Zhao Liu
2023-02-02 9:49 ` [PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-02-02 9:49 ` [PATCH 17/18] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-02-02 9:49 ` [PATCH 18/18] i386: Add new property to control L2 cache topo in CPUID.04H Zhao Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230202094929.343799-14-zhao1.liu@linux.intel.com \
--to=zhao1.liu@linux.intel.com \
--cc=eduardo@habkost.net \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wangyanan55@huawei.com \
--cc=zhao1.liu@intel.com \
--cc=zhenyu.z.wang@intel.com \
--cc=zhuocheng.ding@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.