From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
William Salmon <will.salmon@codethink.co.uk>
Subject: [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support
Date: Fri, 10 Mar 2023 09:11:42 +0000 [thread overview]
Message-ID: <20230310091215.931644-13-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk>
From: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
---
target/riscv/helper.h | 5 +++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvzvkb.c.inc | 38 ++++++++++++++++++++++
target/riscv/vcrypto_helper.c | 21 ++++++++++++
4 files changed, 65 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 841cb43f04..625f9872d0 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1168,3 +1168,8 @@ DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c557c063df..87473a77c0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -921,3 +921,4 @@ vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm
vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm
vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm
vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
+vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc
index f71383e482..7cd114ae71 100644
--- a/target/riscv/insn_trans/trans_rvzvkb.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc
@@ -145,3 +145,41 @@ GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvkb_vx_check)
GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvkb_vv_check)
GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvkb_vx_check)
GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_ZIMM6, vror_vx, rotri, zvkb_vx_check)
+
+#define GEN_OPIV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmr * a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
+ data, fns[s->sew]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+static bool vxrev8_check(DisasContext *s, arg_rmr *a)
+{
+ return s->cfg_ptr->ext_zvkb == true &&
+ require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
+}
+
+GEN_OPIV_TRANS(vbrev8_v, vxrev8_check)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index 30ed9b1270..5d2a995de6 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -93,3 +93,24 @@ GEN_VEXT_VX(vrol_vx_b, 1)
GEN_VEXT_VX(vrol_vx_h, 2)
GEN_VEXT_VX(vrol_vx_w, 4)
GEN_VEXT_VX(vrol_vx_d, 8)
+
+static uint64_t brev8(uint64_t val)
+{
+ val = ((val & 0x5555555555555555ull) << 1)
+ | ((val & 0xAAAAAAAAAAAAAAAAull) >> 1);
+ val = ((val & 0x3333333333333333ull) << 2)
+ | ((val & 0xCCCCCCCCCCCCCCCCull) >> 2);
+ val = ((val & 0x0F0F0F0F0F0F0F0Full) << 4)
+ | ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4);
+
+ return val;
+}
+
+RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8)
+RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8)
+RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8)
+RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8)
+GEN_VEXT_V(vbrev8_v_b, 1)
+GEN_VEXT_V(vbrev8_v_h, 2)
+GEN_VEXT_V(vbrev8_v_w, 4)
+GEN_VEXT_V(vbrev8_v_d, 8)
--
2.39.2
next prev parent reply other threads:[~2023-03-10 9:17 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-10 9:11 [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 01/45] target/riscv: Add zvkb cpu property Lawrence Hunter
2023-03-10 9:11 ` [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 9:11 ` [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 04/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-12 23:40 ` Wilfred Mallawa
2023-03-10 9:11 ` [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 06/45] target/riscv: Add vclmulh.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 07/45] target/riscv: Add vclmulh.vx " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 9:11 ` [PATCH 09/45] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-03-10 9:11 ` [PATCH 10/45] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 10/45] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-03-10 9:11 ` Lawrence Hunter [this message]
2023-03-10 9:11 ` [PATCH 13/45] target/riscv: Add vrev8.v decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 14/45] target/riscv: Add vandn.[vv, vx] " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 14/45] target/riscv: Add vandn.[vv,vx] " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 15/45] target/riscv: Expose zvkb cpu property Lawrence Hunter
2023-03-10 9:11 ` [PATCH 16/45] target/riscv: Add zvkned " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:11 ` [PATCH 18/45] target/riscv: Add vaesef.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 19/45] target/riscv: Add vaesdf.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 20/45] target/riscv: Add vaesdf.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 21/45] target/riscv: Add vaesdm.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 22/45] target/riscv: Add vaesdm.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 23/45] target/riscv: Add vaesz.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 24/45] target/riscv: Add vaesem.vv " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 25/45] target/riscv: Add vaesem.vs " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 26/45] target/riscv: Add vaeskf1.vi " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 27/45] target/riscv: Add vaeskf2.vi " Lawrence Hunter
2023-03-10 9:11 ` [PATCH 28/45] target/riscv: Expose zvkned cpu property Lawrence Hunter
2023-03-10 9:11 ` [PATCH 29/45] target/riscv: Add zvknh cpu properties Lawrence Hunter
2023-03-10 9:12 ` [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 31/45] target/riscv: Add vsha2c[hl].vv " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 32/45] target/riscv: Expose zvknh cpu properties Lawrence Hunter
2023-03-10 9:12 ` [PATCH 33/45] target/riscv: Add zvksh cpu property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 35/45] target/riscv: Add vsm3c.vi " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 36/45] target/riscv: Expose zvksh cpu property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 37/45] target/riscv: Add zvkg " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 38/45] target/riscv: Add vgmul.vv decoding, translation and execution support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 39/45] target/riscv: Add vghsh.vv " Lawrence Hunter
2023-03-10 9:12 ` [PATCH 40/45] target/riscv: Expose zvkg cpu property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 41/45] crypto: Create sm4_subword Lawrence Hunter
2023-03-10 9:12 ` [PATCH 42/45] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-03-10 9:12 ` [PATCH 43/45] target/riscv: Add zvksed cfg property Lawrence Hunter
2023-03-10 9:12 ` [PATCH 44/45] target/riscv: Add Zvksed support Lawrence Hunter
2023-03-10 9:12 ` [PATCH 45/45] target/riscv: Expose Zvksed property Lawrence Hunter
2023-03-21 12:02 ` [PATCH 00/45] Add RISC-V vector cryptographic instruction set support Christoph Müllner
2023-03-23 11:34 ` Lawrence Hunter
2023-03-23 11:36 ` Christoph Müllner
2023-03-10 16:03 Lawrence Hunter
2023-03-10 16:03 ` [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support Lawrence Hunter
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