Re: [PATCH v14 2/6] mfd: Add Renesas RZ/G2L MTU3a core driver

From: Lee Jones <lee@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: "Philipp Zabel" <p.zabel@pengutronix.de>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"William Breathitt Gray" <william.gray@linaro.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Fabrizio Castro" <fabrizio.castro.jz@renesas.com>,
	"Chris Paterson" <chris.paterson2@renesas.com>,
	"Prabhakar Mahadev Lad" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v14 2/6] mfd: Add Renesas RZ/G2L MTU3a core driver
Date: Thu, 16 Mar 2023 15:58:06 +0000	[thread overview]
Message-ID: <20230316155806.GN9667@google.com> (raw)
In-Reply-To: <20230310170654.268047-3-biju.das.jz@bp.renesas.com>

On Fri, 10 Mar 2023, Biju Das wrote:

> The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> the Renesas RZ/G2L family SoCs. It consists of eight 16-bit timer
> channels and one 32-bit timer channel. It supports the following
> functions
>  - Counter
>  - Timer
>  - PWM
>
> The 8/16/32 bit registers are mixed in each channel.
>
> Add MTU3a core driver for RZ/G2L SoC. The core driver shares the
> clk and channel register access for the other child devices like
> Counter, PWM and Clock event.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> Ref:
>  https://patchwork.kernel.org/project/linux-renesas-soc/patch/20230113161753.1073706-3-biju.das.jz@bp.renesas.com/
> v13->v14:
>  * Added helper macros for initializing 8/16/32 channel reg offset table in
>    "drivers/mfd/rz-mtu3.h"
>  * Replaced "off"->offset in read_write()
>  * Replaced __LINUX_RZ_MTU3_H__->__MFD_RZ_MTU3_H__
>  * Added header file device.h and mutex.h
>  * Updated rz_mtu3_request_channel()
>  * Replaced channel_index->channel_number in struct rz_mtu3_channel
>  * Dropped redundant comments.
>  * Renamed channel number macros from RZ_MTU*->RZ_MTU3_CHAN_*
>  * Added core driver specific private data in struct rz_mtu3 and updated the
>    comments. This replaces mmio from struct rz_mtu3.
>  * Started using actual offset in channel reg table and removed ch_reg_offsets table
>    Also simplified the code 8/16/32 bits read_write() and removed base from
>    struct rz_mtu3_channel.
>  * Simplified rz_mtu3_start_stop_ch()/rz_mtu3_is_enabled() by adding helper functions
>    rz_mtu3_get_tstr_offset()/rz_mtu3_get_tstr_bit_pos().
> v12->v13:
>  * Moved RZ_MTU3_TMDR1_* macros from pwm driver to rz-mtu3.h.
> v11->v2:
>  * Moved the core driver from timer to MFD.
>  * Moved header fine from clocksource/rz-mtu3.h->linux/mfd/rz-mtu3.h
>  * Removed Select MFD_CORE option from config.
> v10->v11:
>  * No change.
> v9->v10:
>  * No change.
> v8->v9:
>  * No change.
> v7->v8:
>  * Add locking for RMW on rz_mtu3_shared_reg_update_bit()
>  * Replaced enum rz_mtu3_functions with channel busy flag
>  * Added API for request and release a channel.
> v6->v7:
>  * Added channel specific mutex to avoid races between child devices
>    (for eg: pwm and counter)
>  * Added rz_mtu3_shared_reg_update_bit() to update bit.
> v5->v6:
>  * Updated commit and KConfig description
>  * Selected MFD_CORE to avoid build error if CONFIG_MFD_CORE not set.
>  * Improved error handling in probe().
>  * Updated MODULE_DESCRIPTION and title.
> v4->v5:
>  * Moved core driver from MFD to timer
>  * Child devices instatiated using mfd_add_devices()
> v3->v4:
>  * A single driver that registers both the counter and the pwm functionalities
>    that binds against "renesas,rz-mtu3".
>  * Moved PM handling from child devices to here.
>  * replaced include/linux/mfd/rz-mtu3.h->drivers/mfd/rz-mtu3.h
>  * Removed "remove" callback
> v2->v3:
>  * removed unwanted header files
>  * Added LUT for 32 bit registers as it needed for 32-bit cascade counting.
>  * Exported 32 bit read/write functions.
> v1->v2:
>  * Changed the compatible name
>  * Replaced devm_reset_control_get->devm_reset_control_get_exclusive
>  * Renamed function names rzg2l_mtu3->rz_mtu3 as this is generic IP
>    in RZ family SoC's.
> ---
>  drivers/mfd/Kconfig         |  10 +
>  drivers/mfd/Makefile        |   1 +
>  drivers/mfd/rz-mtu3.c       | 391 ++++++++++++++++++++++++++++++++++++
>  drivers/mfd/rz-mtu3.h       | 147 ++++++++++++++
>  include/linux/mfd/rz-mtu3.h | 241 ++++++++++++++++++++++
>  5 files changed, 790 insertions(+)
>  create mode 100644 drivers/mfd/rz-mtu3.c
>  create mode 100644 drivers/mfd/rz-mtu3.h
>  create mode 100644 include/linux/mfd/rz-mtu3.h

I plan to take this set via MFD once you have  PWM Ack.

For my own reference (apply this as-is to your sign-off block):

Acked-for-MFD-by: Lee Jones <lee@kernel.org>

--
Lee Jones [李琼斯]