From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH for-8.1 v4 13/25] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
Date: Wed, 22 Mar 2023 19:19:52 -0300 [thread overview]
Message-ID: <20230322222004.357013-14-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230322222004.357013-1-dbarboza@ventanamicro.com>
The extremely tedious code that sets cpu->cfg based on misa_ext, and
vice-versa, is scattered around riscv_cpu_validate_set_extensions() and
set_misa().
Introduce helpers to do this work, cleaning up the logic of both
functions a bit. While we're at it, add a note in cpu.h informing that
any future change in MISA RV* bits should also be reflected in the
helpers as well.
We'll want to keep env->misa_ext changes in sync with cpu->cfg during
realize() in the next patches, and both helpers will have a role to play
in that.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 120 ++++++++++++++++++++++++---------------------
target/riscv/cpu.h | 3 +-
2 files changed, 65 insertions(+), 58 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0e56a1c01f..c4f18d0436 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -234,10 +234,69 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
}
}
-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg)
{
- RISCVCPU *cpu;
+ uint32_t ext = 0;
+ if (cfg->ext_i) {
+ ext |= RVI;
+ }
+ if (cfg->ext_e) {
+ ext |= RVE;
+ }
+ if (cfg->ext_m) {
+ ext |= RVM;
+ }
+ if (cfg->ext_a) {
+ ext |= RVA;
+ }
+ if (cfg->ext_f) {
+ ext |= RVF;
+ }
+ if (cfg->ext_d) {
+ ext |= RVD;
+ }
+ if (cfg->ext_c) {
+ ext |= RVC;
+ }
+ if (cfg->ext_s) {
+ ext |= RVS;
+ }
+ if (cfg->ext_u) {
+ ext |= RVU;
+ }
+ if (cfg->ext_h) {
+ ext |= RVH;
+ }
+ if (cfg->ext_v) {
+ ext |= RVV;
+ }
+ if (cfg->ext_j) {
+ ext |= RVJ;
+ }
+
+ return ext;
+}
+
+static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg,
+ uint32_t misa_ext)
+{
+ cfg->ext_i = misa_ext & RVI;
+ cfg->ext_e = misa_ext & RVE;
+ cfg->ext_m = misa_ext & RVM;
+ cfg->ext_a = misa_ext & RVA;
+ cfg->ext_f = misa_ext & RVF;
+ cfg->ext_d = misa_ext & RVD;
+ cfg->ext_v = misa_ext & RVV;
+ cfg->ext_c = misa_ext & RVC;
+ cfg->ext_s = misa_ext & RVS;
+ cfg->ext_u = misa_ext & RVU;
+ cfg->ext_h = misa_ext & RVH;
+ cfg->ext_j = misa_ext & RVJ;
+}
+
+static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+{
env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext;
@@ -251,25 +310,7 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
return;
}
- /*
- * We can't use riscv_cpu_cfg() in this case because it is
- * a read-only inline and we're going to change the values
- * of cpu->cfg.
- */
- cpu = env_archcpu(env);
-
- cpu->cfg.ext_i = ext & RVI;
- cpu->cfg.ext_e = ext & RVE;
- cpu->cfg.ext_m = ext & RVM;
- cpu->cfg.ext_a = ext & RVA;
- cpu->cfg.ext_f = ext & RVF;
- cpu->cfg.ext_d = ext & RVD;
- cpu->cfg.ext_v = ext & RVV;
- cpu->cfg.ext_c = ext & RVC;
- cpu->cfg.ext_s = ext & RVS;
- cpu->cfg.ext_u = ext & RVU;
- cpu->cfg.ext_h = ext & RVH;
- cpu->cfg.ext_j = ext & RVJ;
+ riscv_set_cpucfg_with_misa(&env_archcpu(env)->cfg, ext);
}
#ifndef CONFIG_USER_ONLY
@@ -1153,42 +1194,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
*/
riscv_cpu_disable_priv_spec_isa_exts(cpu);
- if (cpu->cfg.ext_i) {
- ext |= RVI;
- }
- if (cpu->cfg.ext_e) {
- ext |= RVE;
- }
- if (cpu->cfg.ext_m) {
- ext |= RVM;
- }
- if (cpu->cfg.ext_a) {
- ext |= RVA;
- }
- if (cpu->cfg.ext_f) {
- ext |= RVF;
- }
- if (cpu->cfg.ext_d) {
- ext |= RVD;
- }
- if (cpu->cfg.ext_c) {
- ext |= RVC;
- }
- if (cpu->cfg.ext_s) {
- ext |= RVS;
- }
- if (cpu->cfg.ext_u) {
- ext |= RVU;
- }
- if (cpu->cfg.ext_h) {
- ext |= RVH;
- }
- if (cpu->cfg.ext_v) {
- ext |= RVV;
- }
- if (cpu->cfg.ext_j) {
- ext |= RVJ;
- }
+ ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg);
env->misa_ext_mask = env->misa_ext = ext;
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ebe0fff668..2263629332 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,7 +66,8 @@
#define RV(x) ((target_ulong)1 << (x - 'A'))
/*
- * Consider updating set_misa() when adding new
+ * Consider updating riscv_get_misa_ext_with_cpucfg()
+ * and riscv_set_cpucfg_with_misa() when adding new
* MISA bits here.
*/
#define RVI RV('I')
--
2.39.2
next prev parent reply other threads:[~2023-03-22 23:40 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 22:19 [PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions validation Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 01/25] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 02/25] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 03/25] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 04/25] target/riscv: add PRIV_VERSION_LATEST Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 05/25] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 06/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Daniel Henrique Barboza
2023-03-23 1:35 ` LIU Zhiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions() Daniel Henrique Barboza
2023-03-23 1:42 ` LIU Zhiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 08/25] target/riscv/cpu.c: validate extensions before riscv_timer_init() Daniel Henrique Barboza
2023-03-23 1:52 ` LIU Zhiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 09/25] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-03-23 2:02 ` LIU Zhiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 10/25] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Daniel Henrique Barboza
2023-03-23 2:04 ` LIU Zhiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa() Daniel Henrique Barboza
2023-03-23 2:14 ` LIU Zhiwei
2023-03-23 2:18 ` LIU Zhiwei
2023-03-23 23:23 ` Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 12/25] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
2023-03-23 3:22 ` LIU Zhiwei
2023-03-22 22:19 ` Daniel Henrique Barboza [this message]
2023-03-22 22:19 ` [PATCH for-8.1 v4 14/25] target/riscv: add RVG Daniel Henrique Barboza
2023-03-24 14:43 ` liweiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 15/25] target/riscv/cpu.c: split RVG code from validate_set_extensions() Daniel Henrique Barboza
2023-03-24 14:47 ` liweiwei
2023-03-22 22:19 ` [PATCH for-8.1 v4 16/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext() Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 17/25] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext() Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 18/25] target/riscv: error out on priv failure for RVH Daniel Henrique Barboza
2023-03-24 14:56 ` liweiwei
2023-03-28 14:33 ` Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props() Daniel Henrique Barboza
2023-03-22 22:19 ` [PATCH for-8.1 v4 20/25] target/riscv: make validate_misa_ext() use a misa_ext val Daniel Henrique Barboza
2023-03-22 22:20 ` [PATCH for-8.1 v4 21/25] target/riscv: split riscv_cpu_validate_set_extensions() Daniel Henrique Barboza
2023-03-22 22:20 ` [PATCH for-8.1 v4 22/25] target/riscv: use misa_ext val in riscv_cpu_validate_extensions() Daniel Henrique Barboza
2023-03-24 15:06 ` liweiwei
2023-03-22 22:20 ` [PATCH for-8.1 v4 23/25] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-03-24 15:09 ` liweiwei
2023-03-22 22:20 ` [PATCH for-8.1 v4 24/25] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg() Daniel Henrique Barboza
2023-03-24 15:14 ` liweiwei
2023-03-22 22:20 ` [PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa() Daniel Henrique Barboza
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