From: Prabhakar <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 1/2] arm64: dts: renesas: r9a07g054: Add CSI and CRU nodes
Date: Wed, 12 Apr 2023 19:56:07 +0100 [thread overview]
Message-ID: <20230412185608.64628-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20230412185608.64628-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add CSI and CRU nodes to r9a07g054 (RZ/V2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 79 ++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index cc11e5855d62..f87bce02e043 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -623,6 +623,85 @@ sbc: spi@10060000 {
status = "disabled";
};
+ cru: video@10830000 {
+ compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru";
+ reg = <0 0x10830000 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
+ <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
+ <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
+ clock-names = "video", "apb", "axi";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
+ resets = <&cpg R9A07G054_CRU_PRESETN>,
+ <&cpg R9A07G054_CRU_ARESETN>;
+ reset-names = "presetn", "aresetn";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ cruparallel: endpoint@0 {
+ reg = <0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+ crucsi2: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi2cru>;
+ };
+ };
+ };
+ };
+
+ csi2: csi2@10830400 {
+ compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2";
+ reg = <0 0x10830400 0 0xfc00>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
+ <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
+ <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
+ clock-names = "system", "video", "apb";
+ resets = <&cpg R9A07G054_CRU_PRESETN>,
+ <&cpg R9A07G054_CRU_CMN_RSTB>;
+ reset-names = "presetn", "cmn-rstb";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ csi2cru: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&crucsi2>;
+ };
+ };
+ };
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g054-cpg";
reg = <0 0x11010000 0 0x10000>;
--
2.25.1
next prev parent reply other threads:[~2023-04-12 18:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-12 18:56 [PATCH 0/2] RZ/V2L: Add CRU, CSI support Prabhakar
2023-04-12 18:56 ` Prabhakar [this message]
2023-04-20 13:38 ` [PATCH 1/2] arm64: dts: renesas: r9a07g054: Add CSI and CRU nodes Geert Uytterhoeven
2023-04-12 18:56 ` [PATCH 2/2] arm64: dts: renesas: rzv2l-smarc: Enable CRU, CSI support Prabhakar
2023-04-17 8:56 ` Geert Uytterhoeven
2023-04-17 11:04 ` Lad, Prabhakar
2023-04-17 11:37 ` Geert Uytterhoeven
2023-04-20 13:50 ` Geert Uytterhoeven
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