From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Chenyi Qiang <chenyi.qiang@intel.com>,
lei4.wang@intel.com
Subject: [PATCH v4 7/8] target/i386/intel-pt: Define specific PT feature set for IceLake-server, Snowridge and SapphireRapids
Date: Wed, 31 May 2023 04:43:10 -0400 [thread overview]
Message-ID: <20230531084311.3807277-8-xiaoyao.li@intel.com> (raw)
In-Reply-To: <20230531084311.3807277-1-xiaoyao.li@intel.com>
For IceLake-server, it's just the same as using the default PT
feature set since the default one is exact taken from ICX.
For Snowridge and SapphireRapids, define it according to real silicon
capabilities.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
Changes in v4:
- Add Intel PT capabilities for SapphireRapids cpu model;
---
target/i386/cpu.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e47629aff68e..182ba02e2fee 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3699,6 +3699,14 @@ static const X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
/* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
+ .features[FEAT_14_0_EBX] =
+ CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
+ CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC,
+ .features[FEAT_14_0_ECX] =
+ CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
+ CPUID_14_0_ECX_SINGLE_RANGE,
+ .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
+ .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x1fff,
.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
MSR_VMX_BASIC_TRUE_CTLS,
.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
@@ -3869,6 +3877,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_7_1_EAX] =
CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
+ .features[FEAT_14_0_EBX] =
+ CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
+ CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC |
+ CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_PSB_PMI_PRESERVATION,
+ .features[FEAT_14_0_ECX] =
+ CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
+ CPUID_14_0_ECX_SINGLE_RANGE,
+ .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
+ .features[FEAT_14_1_EBX] = 0x003f << 16 | 0x3f,
.features[FEAT_VMX_BASIC] =
MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
.features[FEAT_VMX_ENTRY_CTLS] =
@@ -4105,6 +4122,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
+ .features[FEAT_14_0_EBX] =
+ CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EBX_PSB |
+ CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX_MTC |
+ CPUID_14_0_EBX_PTWRITE | CPUID_14_0_EBX_POWER_EVENT |
+ CPUID_14_0_EBX_PSB_PMI_PRESERVATION,
+ .features[FEAT_14_0_ECX] =
+ CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULTI_ENTRIES |
+ CPUID_14_0_ECX_SINGLE_RANGE | CPUID_14_0_ECX_LIP,
+ .features[FEAT_14_1_EAX] = 0x249 << 16 | 0x2,
+ .features[FEAT_14_1_EBX] = 0x003f << 16 | 0xffff,
.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
MSR_VMX_BASIC_TRUE_CTLS,
.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
--
2.34.1
next prev parent reply other threads:[~2023-05-31 8:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-31 8:43 [PATCH v4 0/8] i386: Make Intel PT configurable Xiaoyao Li
2023-05-31 8:43 ` [PATCH v4 1/8] target/i386: Print CPUID subleaf info for unsupported feature Xiaoyao Li
2023-05-31 8:43 ` [PATCH v4 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK Xiaoyao Li
2023-05-31 8:43 ` [PATCH v4 3/8] target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0x14 Xiaoyao Li
2023-05-31 8:43 ` [PATCH v4 4/8] target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM Xiaoyao Li
2023-05-31 8:43 ` [PATCH v4 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set Xiaoyao Li
2023-05-31 8:43 ` [PATCH v4 6/8] target/i386/intel-pt: Enable host pass through of Intel PT Xiaoyao Li
2023-05-31 8:43 ` Xiaoyao Li [this message]
2023-05-31 8:43 ` [PATCH v4 8/8] target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration Xiaoyao Li
2023-07-03 2:03 ` [PATCH v4 0/8] i386: Make Intel PT configurable Xiaoyao Li
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