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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: linux-usb@vger.kernel.org
Cc: Yehezkel Bernat <YehezkelShB@gmail.com>,
	Michael Jamet <michael.jamet@intel.com>,
	Lukas Wunner <lukas@wunner.de>,
	Andreas Noever <andreas.noever@gmail.com>,
	Gil Fine <gil.fine@linux.intel.com>,
	Christian Kellner <ckellner@redhat.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [PATCH 20/20] thunderbolt: Add test case for 3 DisplayPort tunnels
Date: Wed, 31 May 2023 12:06:45 +0300	[thread overview]
Message-ID: <20230531090645.5573-21-mika.westerberg@linux.intel.com> (raw)
In-Reply-To: <20230531090645.5573-1-mika.westerberg@linux.intel.com>

Intel Barlow Ridge Thunderbolt controller has 3 DP IN adapters. This
allows 3 simultaneus DisplayPort tunnels through either one or two USB4
downstream ports (in any possible configuration). Add test case for
this.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/thunderbolt/test.c | 83 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/drivers/thunderbolt/test.c b/drivers/thunderbolt/test.c
index 24c06e7354cd..9475c6698c7d 100644
--- a/drivers/thunderbolt/test.c
+++ b/drivers/thunderbolt/test.c
@@ -170,6 +170,23 @@ static struct tb_switch *alloc_host_usb4(struct kunit *test)
 	return sw;
 }
 
+static struct tb_switch *alloc_host_br(struct kunit *test)
+{
+	struct tb_switch *sw;
+
+	sw = alloc_host_usb4(test);
+	if (!sw)
+		return NULL;
+
+	sw->ports[10].config.type = TB_TYPE_DP_HDMI_IN;
+	sw->ports[10].config.max_in_hop_id = 9;
+	sw->ports[10].config.max_out_hop_id = 9;
+	sw->ports[10].cap_adap = -1;
+	sw->ports[10].disabled = false;
+
+	return sw;
+}
+
 static struct tb_switch *alloc_dev_default(struct kunit *test,
 					   struct tb_switch *parent,
 					   u64 route, bool bonded)
@@ -1583,6 +1600,71 @@ static void tb_test_tunnel_dp_max_length(struct kunit *test)
 	tb_tunnel_free(tunnel);
 }
 
+static void tb_test_tunnel_3dp(struct kunit *test)
+{
+	struct tb_switch *host, *dev1, *dev2, *dev3, *dev4, *dev5;
+	struct tb_port *in1, *in2, *in3, *out1, *out2, *out3;
+	struct tb_tunnel *tunnel1, *tunnel2, *tunnel3;
+
+	/*
+	 * Create 3 DP tunnels from Host to Devices #2, #5 and #4.
+	 *
+	 *          [Host]
+	 *           3 |
+	 *           1 |
+	 *         [Device #1]
+	 *       3 /   | 5  \ 7
+	 *      1 /    |     \ 1
+	 * [Device #2] |    [Device #4]
+	 *             | 1
+	 *         [Device #3]
+	 *             | 5
+	 *             | 1
+	 *         [Device #5]
+	 */
+	host = alloc_host_br(test);
+	dev1 = alloc_dev_default(test, host, 0x3, true);
+	dev2 = alloc_dev_default(test, dev1, 0x303, true);
+	dev3 = alloc_dev_default(test, dev1, 0x503, true);
+	dev4 = alloc_dev_default(test, dev1, 0x703, true);
+	dev5 = alloc_dev_default(test, dev3, 0x50503, true);
+
+	in1 = &host->ports[5];
+	in2 = &host->ports[6];
+	in3 = &host->ports[10];
+
+	out1 = &dev2->ports[13];
+	out2 = &dev5->ports[13];
+	out3 = &dev4->ports[14];
+
+	tunnel1 = tb_tunnel_alloc_dp(NULL, in1, out1, 1, 0, 0);
+	KUNIT_ASSERT_TRUE(test, tunnel1 != NULL);
+	KUNIT_EXPECT_EQ(test, tunnel1->type, TB_TUNNEL_DP);
+	KUNIT_EXPECT_PTR_EQ(test, tunnel1->src_port, in1);
+	KUNIT_EXPECT_PTR_EQ(test, tunnel1->dst_port, out1);
+	KUNIT_ASSERT_EQ(test, tunnel1->npaths, 3);
+	KUNIT_ASSERT_EQ(test, tunnel1->paths[0]->path_length, 3);
+
+	tunnel2 = tb_tunnel_alloc_dp(NULL, in2, out2, 1, 0, 0);
+	KUNIT_ASSERT_TRUE(test, tunnel2 != NULL);
+	KUNIT_EXPECT_EQ(test, tunnel2->type, TB_TUNNEL_DP);
+	KUNIT_EXPECT_PTR_EQ(test, tunnel2->src_port, in2);
+	KUNIT_EXPECT_PTR_EQ(test, tunnel2->dst_port, out2);
+	KUNIT_ASSERT_EQ(test, tunnel2->npaths, 3);
+	KUNIT_ASSERT_EQ(test, tunnel2->paths[0]->path_length, 4);
+
+	tunnel3 = tb_tunnel_alloc_dp(NULL, in3, out3, 1, 0, 0);
+	KUNIT_ASSERT_TRUE(test, tunnel3 != NULL);
+	KUNIT_EXPECT_EQ(test, tunnel3->type, TB_TUNNEL_DP);
+	KUNIT_EXPECT_PTR_EQ(test, tunnel3->src_port, in3);
+	KUNIT_EXPECT_PTR_EQ(test, tunnel3->dst_port, out3);
+	KUNIT_ASSERT_EQ(test, tunnel3->npaths, 3);
+	KUNIT_ASSERT_EQ(test, tunnel3->paths[0]->path_length, 3);
+
+	tb_tunnel_free(tunnel2);
+	tb_tunnel_free(tunnel1);
+}
+
 static void tb_test_tunnel_usb3(struct kunit *test)
 {
 	struct tb_switch *host, *dev1, *dev2;
@@ -2790,6 +2872,7 @@ static struct kunit_case tb_test_cases[] = {
 	KUNIT_CASE(tb_test_tunnel_dp_chain),
 	KUNIT_CASE(tb_test_tunnel_dp_tree),
 	KUNIT_CASE(tb_test_tunnel_dp_max_length),
+	KUNIT_CASE(tb_test_tunnel_3dp),
 	KUNIT_CASE(tb_test_tunnel_port_on_path),
 	KUNIT_CASE(tb_test_tunnel_usb3),
 	KUNIT_CASE(tb_test_tunnel_dma),
-- 
2.39.2


      parent reply	other threads:[~2023-05-31  9:08 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-31  9:06 [PATCH 00/20] thunderbolt: Initial USB4 v2 support Mika Westerberg
2023-05-31  9:06 ` [PATCH 01/20] thunderbolt: Ignore data CRC mismatch for USB4 routers Mika Westerberg
2023-05-31  9:06 ` [PATCH 02/20] thunderbolt: Do not touch lane 1 adapter path config space Mika Westerberg
2023-05-31  9:06 ` [PATCH 03/20] thunderbolt: Identify USB4 v2 routers Mika Westerberg
2023-05-31 12:00   ` Yehezkel Bernat
2023-06-02  8:18     ` Mika Westerberg
2023-05-31  9:06 ` [PATCH 04/20] thunderbolt: Add support for USB4 v2 80 Gb/s link Mika Westerberg
2023-05-31  9:06 ` [PATCH 05/20] thunderbolt: Add the new USB4 v2 notification types Mika Westerberg
2023-05-31  9:06 ` [PATCH 06/20] thunderbolt: Reset USB4 v2 host router Mika Westerberg
2023-05-31  9:06 ` [PATCH 07/20] thunderbolt: Announce USB4 v2 connection manager support Mika Westerberg
2023-05-31  9:06 ` [PATCH 08/20] thunderbolt: Enable USB4 v2 PCIe TLP/DLLP extended encapsulation Mika Westerberg
2023-05-31  9:06 ` [PATCH 09/20] thunderbolt: Add two additional double words for adapters TMU for USB4 v2 routers Mika Westerberg
2023-05-31  9:06 ` [PATCH 10/20] thunderbolt: Fix DisplayPort IN adapter capability length " Mika Westerberg
2023-05-31  9:06 ` [PATCH 11/20] thunderbolt: Fix PCIe " Mika Westerberg
2023-05-31  9:06 ` [PATCH 12/20] thunderbolt: Add Intel Barlow Ridge PCI ID Mika Westerberg
2023-05-31  9:06 ` [PATCH 13/20] thunderbolt: Limit Intel Barlow Ridge USB3 bandwidth Mika Westerberg
2023-05-31  9:06 ` [PATCH 14/20] thunderbolt: Move constants related to NVM into nvm.c Mika Westerberg
2023-05-31  9:06 ` [PATCH 15/20] thunderbolt: Increase NVM_MAX_SIZE to support Intel Barlow Ridge controller Mika Westerberg
2023-05-31  9:06 ` [PATCH 16/20] thunderbolt: Add support for enhanced uni-directional TMU mode Mika Westerberg
2023-05-31  9:06 ` [PATCH 17/20] thunderbolt: Enable CL2 low power state Mika Westerberg
2023-05-31  9:06 ` [PATCH 18/20] thunderbolt: Make bandwidth allocation mode function names consistent Mika Westerberg
2023-05-31  9:06 ` [PATCH 19/20] thunderbolt: Add DisplayPort 2.x tunneling support Mika Westerberg
2023-05-31  9:06 ` Mika Westerberg [this message]

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