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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com
Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
	linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, steev@kali.org,
	quic_srichara@quicinc.com,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v3 7/8] PCI: qcom: Do not advertise hotplug capability for IP v1.0.0
Date: Thu,  1 Jun 2023 22:08:59 +0530	[thread overview]
Message-ID: <20230601163900.15500-8-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org>

SoCs making use of Qcom PCIe controller IP v1.0.0 do not support hotplug
functionality. But the hotplug capability bit is set by default in the
hardware. This causes the kernel PCI core to register hotplug service for
the controller and send hotplug commands to it. But those commands will
timeout generating messages as below during boot and suspend/resume.

[    5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
[    5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago)
[    7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago)
[    7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago)

This not only spams the console output but also induces a delay of a
couple of seconds. To fix this issue, let's clear the HPC bit in
PCI_EXP_SLTCAP register as a part of the post init sequence to not
advertise the hotplug capability for the controller.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index e6db9e551752..612266fb849a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -521,6 +521,8 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
 	}
 
+	qcom_pcie_clear_hpc(pcie->pci);
+
 	return 0;
 }
 
-- 
2.25.1


  parent reply	other threads:[~2023-06-01 16:40 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-01 16:38 [PATCH v3 0/8] PCI: qcom: Do not advertise hotplug capability Manivannan Sadhasivam
2023-06-01 16:38 ` [PATCH v3 1/8] PCI: qcom: Use DWC helpers for modifying the read-only DBI registers Manivannan Sadhasivam
2023-06-12 12:46   ` Lorenzo Pieralisi
2023-06-01 16:38 ` [PATCH v3 2/8] PCI: qcom: Disable write access to read only registers for IP v2.9.0 Manivannan Sadhasivam
2023-06-01 16:38 ` [PATCH v3 3/8] PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0 Manivannan Sadhasivam
2023-06-01 16:38 ` [PATCH v3 4/8] PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 Manivannan Sadhasivam
2023-06-01 16:38 ` [PATCH v3 5/8] PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 Manivannan Sadhasivam
2023-06-01 16:38 ` [PATCH v3 6/8] PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 Manivannan Sadhasivam
2023-06-01 16:38 ` Manivannan Sadhasivam [this message]
2023-06-01 16:39 ` [PATCH v3 8/8] PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 Manivannan Sadhasivam

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