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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 37/52] target/ppc: Inline gen_icount_io_start()
Date: Mon,  5 Jun 2023 13:15:33 -0700	[thread overview]
Message-ID: <20230605201548.1596865-38-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org>

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Now that gen_icount_io_start() is a simple wrapper to
translator_io_start(), inline it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230602095439.48102-1-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c                 | 63 ++++++++++++--------------
 target/ppc/power8-pmu-regs.c.inc       | 10 ++--
 target/ppc/translate/branch-impl.c.inc |  2 +-
 3 files changed, 35 insertions(+), 40 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 519f66bb05..37fd431870 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -296,15 +296,10 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_icount_io_start(DisasContext *ctx)
-{
-    translator_io_start(&ctx->base);
-}
-
 #if !defined(CONFIG_USER_ONLY)
 static void gen_ppc_maybe_interrupt(DisasContext *ctx)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_ppc_maybe_interrupt(cpu_env);
 }
 #endif
@@ -541,13 +536,13 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
 #if !defined(CONFIG_USER_ONLY)
 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
 }
 
 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
 }
 #endif
@@ -556,13 +551,13 @@ void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
 /* Time base */
 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
 }
 
 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
 }
 
@@ -579,13 +574,13 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
 #if !defined(CONFIG_USER_ONLY)
 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
 }
 
@@ -602,44 +597,44 @@ void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
 #if defined(TARGET_PPC64)
 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
 }
 
 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
 }
 
 /* HDECR */
 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
 }
 
 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
 }
 
 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
 }
 
@@ -784,19 +779,19 @@ void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
 #if !defined(CONFIG_USER_ONLY)
 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
 }
 
 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_store_spr(sprn, cpu_gpr[gprn]);
     gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
     /* We must stop translation as we may have rebooted */
@@ -805,19 +800,19 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
 
 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
 }
 
@@ -830,13 +825,13 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
 
 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
 }
 
 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
 }
 #endif
@@ -2462,7 +2457,7 @@ static void gen_darn(DisasContext *ctx)
     if (l > 2) {
         tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
     } else {
-        gen_icount_io_start(ctx);
+        translator_io_start(&ctx->base);
         if (l == 0) {
             gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
         } else {
@@ -4056,7 +4051,7 @@ static void pmu_count_insns(DisasContext *ctx)
      * running with icount and we do not handle it beforehand,
      * the helper can trigger a 'bad icount read'.
      */
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
 
     /* Avoid helper calls when only PMC5-6 are enabled. */
     if (!ctx->pmc_other) {
@@ -4369,7 +4364,7 @@ static void gen_rfi(DisasContext *ctx)
     }
     /* Restore CPU state */
     CHK_SV(ctx);
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_update_cfar(ctx, ctx->cia);
     gen_helper_rfi(cpu_env);
     ctx->base.is_jmp = DISAS_EXIT;
@@ -4384,7 +4379,7 @@ static void gen_rfid(DisasContext *ctx)
 #else
     /* Restore CPU state */
     CHK_SV(ctx);
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_update_cfar(ctx, ctx->cia);
     gen_helper_rfid(cpu_env);
     ctx->base.is_jmp = DISAS_EXIT;
@@ -4399,7 +4394,7 @@ static void gen_rfscv(DisasContext *ctx)
 #else
     /* Restore CPU state */
     CHK_SV(ctx);
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_update_cfar(ctx, ctx->cia);
     gen_helper_rfscv(cpu_env);
     ctx->base.is_jmp = DISAS_EXIT;
@@ -4724,7 +4719,7 @@ static void gen_mtmsrd(DisasContext *ctx)
     t0 = tcg_temp_new();
     t1 = tcg_temp_new();
 
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
 
     if (ctx->opcode & 0x00010000) {
         /* L=1 form only updates EE and RI */
@@ -4764,7 +4759,7 @@ static void gen_mtmsr(DisasContext *ctx)
     t0 = tcg_temp_new();
     t1 = tcg_temp_new();
 
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     if (ctx->opcode & 0x00010000) {
         /* L=1 form only updates EE and RI */
         mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index d900e13cad..c82feedaff 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -103,9 +103,9 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val)
     /*
      * helper_store_mmcr0 will make clock based operations that
      * will cause 'bad icount read' errors if we do not execute
-     * gen_icount_io_start() beforehand.
+     * translator_io_start() beforehand.
      */
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_mmcr0(cpu_env, val);
 
     /*
@@ -179,7 +179,7 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
 {
     TCGv_i32 t_sprn = tcg_constant_i32(sprn);
 
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
 }
 
@@ -212,7 +212,7 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t_sprn = tcg_constant_i32(sprn);
 
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
 }
 
@@ -248,7 +248,7 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
 
 void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
 {
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]);
 }
 #else
diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc
index 29cfa11854..f9931b9d73 100644
--- a/target/ppc/translate/branch-impl.c.inc
+++ b/target/ppc/translate/branch-impl.c.inc
@@ -16,7 +16,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
 {
     REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
 
-    gen_icount_io_start(ctx);
+    translator_io_start(&ctx->base);
     gen_update_cfar(ctx, ctx->cia);
     gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
 
-- 
2.34.1



  parent reply	other threads:[~2023-06-05 20:20 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-05 20:14 [PULL 00/52] tcg patch queue Richard Henderson
2023-06-05 20:14 ` [PULL 01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL Richard Henderson
2023-06-05 20:14 ` [PULL 02/52] tcg/riscv: " Richard Henderson
2023-06-05 20:14 ` [PULL 03/52] tcg/s390x: " Richard Henderson
2023-06-05 20:15 ` [PULL 04/52] tcg/sparc64: " Richard Henderson
2023-06-05 20:15 ` [PULL 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h Richard Henderson
2023-06-05 20:15 ` [PULL 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits Richard Henderson
2023-06-05 20:15 ` [PULL 07/52] tcg: Add tlb_fast_offset to TCGContext Richard Henderson
2023-06-05 20:15 ` [PULL 08/52] target/avr: Add missing includes of qemu/error-report.h Richard Henderson
2023-06-05 20:15 ` [PULL 09/52] target/*: Add missing includes of tcg/debug-assert.h Richard Henderson
2023-06-05 20:15 ` [PULL 10/52] *: Add missing includes of tcg/tcg.h Richard Henderson
2023-06-05 20:15 ` [PULL 11/52] tcg: Split out tcg-target-reg-bits.h Richard Henderson
2023-06-05 20:15 ` [PULL 12/52] target/arm: Fix test of TCG_OVERSIZED_GUEST Richard Henderson
2023-06-05 20:15 ` [PULL 13/52] tcg: Split out tcg/oversized-guest.h Richard Henderson
2023-06-05 20:15 ` [PULL 14/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h Richard Henderson
2023-06-05 20:15 ` [PULL 15/52] tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h Richard Henderson
2023-06-05 20:15 ` [PULL 16/52] target/arm: Include helper-gen.h in translator.h Richard Henderson
2023-06-05 20:15 ` [PULL 17/52] target/hexagon: Include helper-gen.h where needed Richard Henderson
2023-06-05 20:15 ` [PULL 18/52] tcg: Remove outdated comments in helper-head.h Richard Henderson
2023-06-05 20:15 ` [PULL 19/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h Richard Henderson
2023-06-05 20:15 ` [PULL 20/52] tcg: Pass TCGHelperInfo to tcg_gen_callN Richard Henderson
2023-06-05 20:15 ` [PULL 21/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line Richard Henderson
2023-06-05 20:15 ` [PULL 22/52] tcg: Split tcg_gen_callN Richard Henderson
2023-06-05 20:15 ` [PULL 23/52] tcg: Split helper-gen.h Richard Henderson
2023-06-05 20:15 ` [PULL 24/52] tcg: Split helper-proto.h Richard Henderson
2023-06-05 20:15 ` [PULL 25/52] target/sh4: Emit insn_start for each insn in gUSA region Richard Henderson
2023-06-05 20:15 ` [PULL 26/52] tcg: Add insn_start_words to TCGContext Richard Henderson
2023-06-05 20:15 ` [PULL 27/52] tcg: Add guest_mo " Richard Henderson
2023-06-05 20:15 ` [PULL 28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits Richard Henderson
2023-06-05 20:15 ` [PULL 29/52] tcg: Split tcg/tcg-op-gvec.h Richard Henderson
2023-06-05 20:15 ` [PULL 30/52] tcg: Remove NO_CPU_IO_DEFS Richard Henderson
2023-06-05 20:15 ` [PULL 31/52] exec-all: Widen tb_page_addr_t for user-only Richard Henderson
2023-06-05 20:15 ` [PULL 32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits Richard Henderson
2023-07-11 16:42   ` Peter Maydell
2023-06-05 20:15 ` [PULL 33/52] tcg: Spit out exec/translation-block.h Richard Henderson
2023-06-05 20:15 ` [PULL 34/52] include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE Richard Henderson
2023-06-05 20:15 ` [PULL 35/52] accel/tcg: Move most of gen-icount.h into translator.c Richard Henderson
2023-06-05 20:15 ` [PULL 36/52] accel/tcg: Introduce translator_io_start Richard Henderson
2023-06-05 20:15 ` Richard Henderson [this message]
2023-06-05 20:15 ` [PULL 38/52] accel/tcg: Move translator_fake_ldb out of line Richard Henderson
2023-06-05 20:15 ` [PULL 39/52] target/arm: Tidy helpers for translation Richard Henderson
2023-06-05 20:15 ` [PULL 40/52] target/mips: " Richard Henderson
2023-06-05 20:15 ` [PULL 41/52] target/*: Add missing includes of exec/translation-block.h Richard Henderson
2023-06-05 20:15 ` [PULL 42/52] target/arm: Add missing include of exec/exec-all.h Richard Henderson
2023-06-05 20:15 ` [PULL 43/52] accel/tcg: Tidy includes for translator.[ch] Richard Henderson
2023-06-05 20:15 ` [PULL 44/52] tcg: Fix PAGE/PROT confusion Richard Henderson
2023-06-05 20:15 ` [PULL 45/52] tcg: Move env defines out of NEED_CPU_H in helper-head.h Richard Henderson
2023-06-05 20:15 ` [PULL 46/52] tcg: Remove target-specific headers from tcg.[ch] Richard Henderson
2023-06-05 20:15 ` [PULL 47/52] plugins: Move plugin_insn_append to translator.c Richard Henderson
2023-06-05 20:15 ` [PULL 48/52] plugins: Drop unused headers from exec/plugin-gen.h Richard Henderson
2023-06-05 20:15 ` [PULL 49/52] exec/poison: Do not poison CONFIG_SOFTMMU Richard Henderson
2023-06-20 18:01   ` Peter Maydell
2023-06-21  5:12     ` Richard Henderson
2023-06-05 20:15 ` [PULL 50/52] tcg: Build once for system and once for user-only Richard Henderson
2023-06-05 20:15 ` [PULL 51/52] accel/tcg: Unmap perf_marker Richard Henderson
2023-06-05 20:15 ` [PULL 52/52] tcg/tcg-op-vec: Remove left over _link_error() definitions Richard Henderson
2023-06-05 21:37 ` [PULL 00/52] tcg patch queue Richard Henderson

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