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From: Manivannan Sadhasivam <mani@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: "Bjorn Andersson" <andersson@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Stanimir Varbanov" <svarbanov@mm-sol.com>,
	"Andrew Murray" <amurray@thegoodpenguin.co.uk>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Marijn Suijten" <marijn.suijten@somainline.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/4] PCI: qcom: Read back PARF_LTSSM register
Date: Tue, 2 Jan 2024 22:35:29 +0530	[thread overview]
Message-ID: <20240102170529.GE4917@thinkpad> (raw)
In-Reply-To: <20231227-topic-8280_pcie-v1-3-095491baf9e4@linaro.org>

On Wed, Dec 27, 2023 at 11:17:21PM +0100, Konrad Dybcio wrote:
> To ensure write completion, read the PARF_LTSSM register after setting
> the LTSSM enable bit before polling for "link up".
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

I'd consider this as a bug since if the LTSSM write gets cached in Write Buffer,
then the polling time becomes wrong in dw_pcie_wait_for_link(), leading to
false link_up failure.

Although both of the write/read (LTSSM in qcom_pcie_2_3_2_ltssm_enable(), and
PCI_EXP_LNKSTA in qcom_pcie_link_up()) belong to PCIe domain, they belong to
different regions (PARF, DBI). So I'm not sure we can safely ignore the write
completion issue. So,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a02dc197c495..3d77269e70da 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -540,6 +540,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
>  	val = readl(pcie->parf + PARF_LTSSM);
>  	val |= LTSSM_EN;
>  	writel(val, pcie->parf + PARF_LTSSM);
> +	readl(pcie->parf + PARF_LTSSM);
>  }
>  
>  static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
> 
> -- 
> 2.43.0
> 

-- 
மணிவண்ணன் சதாசிவம்

  reply	other threads:[~2024-01-02 17:05 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-27 22:17 [PATCH 0/4] Qualcomm PCIe RC shutdown & reinit Konrad Dybcio
2023-12-27 22:17 ` [PATCH 1/4] PCI: qcom: Reshuffle reset logic in 2_7_0 .init Konrad Dybcio
2023-12-29 14:04   ` Johan Hovold
2023-12-29 15:01     ` Konrad Dybcio
2023-12-29 15:29       ` Johan Hovold
2023-12-30  1:16         ` Konrad Dybcio
2024-01-01 17:31           ` Manivannan Sadhasivam
2024-01-02 10:17           ` Johan Hovold
2024-01-02 17:03             ` Konrad Dybcio
2024-01-03 10:40               ` Johan Hovold
2024-01-03 12:11                 ` Konrad Dybcio
2023-12-29 15:46     ` Bjorn Helgaas
2023-12-30 22:11       ` Konrad Dybcio
2023-12-27 22:17 ` [PATCH 2/4] PCI: qcom: Cache last icc bandwidth Konrad Dybcio
2023-12-27 22:17 ` [PATCH 3/4] PCI: qcom: Read back PARF_LTSSM register Konrad Dybcio
2024-01-02 17:05   ` Manivannan Sadhasivam [this message]
2023-12-27 22:17 ` [PATCH 4/4] PCI: qcom: Implement RC shutdown/power up Konrad Dybcio
2023-12-28 15:12   ` kernel test robot
2023-12-29  3:42   ` kernel test robot
2024-01-02 17:07   ` Manivannan Sadhasivam

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