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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH v2 5.10.y-cip 12/44] dma-mapping: make the global coherent pool conditional
Date: Tue,  6 Feb 2024 12:27:02 +0000	[thread overview]
Message-ID: <20240206122734.13477-13-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20240206122734.13477-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Christoph Hellwig <hch@lst.de>

commit 22f9feb49950885cdb6e37513f134d154175e743 upstream.

Only build the code to support the global coherent pool if support for
it is enabled.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Dillon Min <dillon.minfei@gmail.com>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
 include/linux/dma-map-ops.h | 18 ++++++++------
 kernel/dma/coherent.c       | 49 ++++++++++++++++++++-----------------
 2 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index e60776bcc2643..411d47bd0dbc9 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -171,13 +171,6 @@ int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size,
 int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr);
 int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma,
 		void *cpu_addr, size_t size, int *ret);
-
-void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
-		dma_addr_t *dma_handle);
-int dma_release_from_global_coherent(int order, void *vaddr);
-int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
-		size_t size, int *ret);
-int dma_init_global_coherent(phys_addr_t phys_addr, size_t size);
 #else
 static inline int dma_declare_coherent_memory(struct device *dev,
 		phys_addr_t phys_addr, dma_addr_t device_addr, size_t size)
@@ -189,7 +182,16 @@ static inline int dma_declare_coherent_memory(struct device *dev,
 #define dma_release_from_dev_coherent(dev, order, vaddr) (0)
 #define dma_mmap_from_dev_coherent(dev, vma, vaddr, order, ret) (0)
 static inline void dma_release_coherent_memory(struct device *dev) { }
+#endif /* CONFIG_DMA_DECLARE_COHERENT */
 
+#ifdef CONFIG_DMA_GLOBAL_POOL
+void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
+		dma_addr_t *dma_handle);
+int dma_release_from_global_coherent(int order, void *vaddr);
+int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
+		size_t size, int *ret);
+int dma_init_global_coherent(phys_addr_t phys_addr, size_t size);
+#else
 static inline void *dma_alloc_from_global_coherent(struct device *dev,
 		ssize_t size, dma_addr_t *dma_handle)
 {
@@ -204,7 +206,7 @@ static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma,
 {
 	return 0;
 }
-#endif /* CONFIG_DMA_DECLARE_COHERENT */
+#endif /* CONFIG_DMA_GLOBAL_POOL */
 
 int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
index 73ab12254747c..60da8ea474b9a 100644
--- a/kernel/dma/coherent.c
+++ b/kernel/dma/coherent.c
@@ -20,8 +20,6 @@ struct dma_coherent_mem {
 	bool		use_dev_dma_pfn_offset;
 };
 
-static struct dma_coherent_mem *dma_coherent_default_memory __ro_after_init;
-
 static inline struct dma_coherent_mem *dev_get_coherent_memory(struct device *dev)
 {
 	if (dev && dev->dma_mem)
@@ -199,16 +197,6 @@ int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size,
 	return 1;
 }
 
-void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
-				     dma_addr_t *dma_handle)
-{
-	if (!dma_coherent_default_memory)
-		return NULL;
-
-	return __dma_alloc_from_coherent(dev, dma_coherent_default_memory, size,
-					 dma_handle);
-}
-
 static int __dma_release_from_coherent(struct dma_coherent_mem *mem,
 				       int order, void *vaddr)
 {
@@ -244,15 +232,6 @@ int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr)
 	return __dma_release_from_coherent(mem, order, vaddr);
 }
 
-int dma_release_from_global_coherent(int order, void *vaddr)
-{
-	if (!dma_coherent_default_memory)
-		return 0;
-
-	return __dma_release_from_coherent(dma_coherent_default_memory, order,
-			vaddr);
-}
-
 static int __dma_mmap_from_coherent(struct dma_coherent_mem *mem,
 		struct vm_area_struct *vma, void *vaddr, size_t size, int *ret)
 {
@@ -298,6 +277,28 @@ int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma,
 	return __dma_mmap_from_coherent(mem, vma, vaddr, size, ret);
 }
 
+#ifdef CONFIG_DMA_GLOBAL_POOL
+static struct dma_coherent_mem *dma_coherent_default_memory __ro_after_init;
+
+void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
+				     dma_addr_t *dma_handle)
+{
+	if (!dma_coherent_default_memory)
+		return NULL;
+
+	return __dma_alloc_from_coherent(dev, dma_coherent_default_memory, size,
+					 dma_handle);
+}
+
+int dma_release_from_global_coherent(int order, void *vaddr)
+{
+	if (!dma_coherent_default_memory)
+		return 0;
+
+	return __dma_release_from_coherent(dma_coherent_default_memory, order,
+			vaddr);
+}
+
 int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *vaddr,
 				   size_t size, int *ret)
 {
@@ -319,6 +320,7 @@ int dma_init_global_coherent(phys_addr_t phys_addr, size_t size)
 	pr_info("DMA: default coherent area is set\n");
 	return 0;
 }
+#endif /* CONFIG_DMA_GLOBAL_POOL */
 
 /*
  * Support for reserved memory regions defined in device tree
@@ -328,7 +330,9 @@ int dma_init_global_coherent(phys_addr_t phys_addr, size_t size)
 #include <linux/of_fdt.h>
 #include <linux/of_reserved_mem.h>
 
+#ifdef CONFIG_DMA_GLOBAL_POOL
 static struct reserved_mem *dma_reserved_default_memory __initdata;
+#endif
 
 static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev)
 {
@@ -385,6 +389,7 @@ static int __init rmem_dma_setup(struct reserved_mem *rmem)
 	return 0;
 }
 
+#ifdef CONFIG_DMA_GLOBAL_POOL
 static int __init dma_init_reserved_memory(void)
 {
 	if (!dma_reserved_default_memory)
@@ -392,8 +397,8 @@ static int __init dma_init_reserved_memory(void)
 	return dma_init_global_coherent(dma_reserved_default_memory->base,
 					dma_reserved_default_memory->size);
 }
-
 core_initcall(dma_init_reserved_memory);
+#endif /* CONFIG_DMA_GLOBAL_POOL */
 
 RESERVEDMEM_OF_DECLARE(dma, "shared-dma-pool", rmem_dma_setup);
 #endif
-- 
2.34.1



  parent reply	other threads:[~2024-02-06 12:28 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-06 12:26 [PATCH v2 5.10.y-cip 00/44] Add support for Renesas RZ/Five RISC-V SoC Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 01/44] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 02/44] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into " Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 03/44] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 04/44] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 05/44] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 06/44] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 07/44] riscv: Kconfig: Enable cpufreq kconfig menu Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 08/44] dma-direct: add support for dma_coherent_default_memory Lad Prabhakar
2024-02-06 12:26 ` [PATCH v2 5.10.y-cip 09/44] dma-mapping: allow using the global coherent pool for !ARM Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 10/44] dma-mapping: simplify dma_init_coherent_memory Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 11/44] dma-mapping: add a dma_init_global_coherent helper Lad Prabhakar
2024-02-06 12:27 ` Lad Prabhakar [this message]
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 13/44] of: also handle dma-noncoherent in of_dma_is_coherent() Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 14/44] of/irq: Use interrupts-extended to find parent Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 15/44] irqchip/sifive-plic: Improve naming scheme for per context offsets Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 16/44] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 17/44] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 18/44] irqchip/sifive-plic: Make better use of the effective affinity mask Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 19/44] irqchip/sifive-plic: Separate the enable and mask operations Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 20/44] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 21/44] clocksource/drivers/riscv: Increase the clock source rating Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 22/44] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 23/44] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_RENESAS Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 24/44] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 25/44] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 26/44] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 27/44] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 28/44] soc: renesas: Identify RZ/Five SoC Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 29/44] clk: renesas: r9a07g043: Add support for " Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 30/44] cache: Add L2 cache management for Andes AX45MP RISC-V core Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 31/44] cache: ax45mp_cache: Add non coherent support Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 32/44] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 33/44] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 34/44] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 35/44] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 36/44] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 37/44] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 38/44] riscv: dts: renesas: rzfive-smarc-som: Enable WDT Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 39/44] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 40/44] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 41/44] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 42/44] riscv: dts: renesas: r9a07g043f: Add L2 cache node Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 43/44] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Lad Prabhakar
2024-02-06 12:27 ` [PATCH v2 5.10.y-cip 44/44] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Lad Prabhakar
2024-02-06 17:51 ` [PATCH v2 5.10.y-cip 00/44] Add support for Renesas RZ/Five RISC-V SoC Pavel Machek

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