Re: [PATCH v2 1/2] dt-bindings: iio: adc: add ad7944 ADCs

From: Rob Herring <robh@kernel.org>
To: David Lechner <dlechner@baylibre.com>
Cc: linux-iio@vger.kernel.org,
	"Michael Hennerich" <Michael.Hennerich@analog.com>,
	"Jonathan Cameron" <jic23@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Nuno Sá" <nuno.sa@analog.com>,
	"Liam Girdwood" <lgirdwood@gmail.com>,
	"Mark Brown" <broonie@kernel.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: iio: adc: add ad7944 ADCs
Date: Wed, 21 Feb 2024 08:22:26 -0700	[thread overview]
Message-ID: <20240221152226.GA2868707-robh@kernel.org> (raw)
In-Reply-To: <20240216-ad7944-mainline-v2-1-7eb69651e592@baylibre.com>

On Fri, Feb 16, 2024 at 01:46:18PM -0600, David Lechner wrote:
> This adds a new binding for the Analog Devices, Inc. AD7944, AD7985, and
> AD7986 ADCs.
> 
> Signed-off-by: David Lechner <dlechner@baylibre.com>
> ---
>  .../devicetree/bindings/iio/adc/adi,ad7944.yaml    | 204 +++++++++++++++++++++
>  MAINTAINERS                                        |   8 +
>  2 files changed, 212 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml
> new file mode 100644
> index 000000000000..61ee81326660
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml
> @@ -0,0 +1,204 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/adi,ad7944.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices PulSAR LFCSP Analog to Digital Converters
> +
> +maintainers:
> +  - Michael Hennerich <Michael.Hennerich@analog.com>
> +  - Nuno Sá <nuno.sa@analog.com>
> +
> +description: |
> +  A family of pin-compatible single channel differential analog to digital
> +  converters with SPI support in a LFCSP package.
> +
> +  * https://www.analog.com/en/products/ad7944.html
> +  * https://www.analog.com/en/products/ad7985.html
> +  * https://www.analog.com/en/products/ad7986.html
> +
> +$ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - adi,ad7944
> +      - adi,ad7985
> +      - adi,ad7986
> +
> +  reg:
> +    maxItems: 1
> +
> +  spi-max-frequency:
> +    maximum: 111111111
> +
> +  spi-cpol: true
> +  spi-cpha: true
> +
> +  adi,spi-mode:
> +    $ref: /schemas/types.yaml#/definitions/string
> +    enum: [ single, multi, chain ]
> +    default: multi
> +    description: |
> +      * single: The datasheet calls this "3-wire mode". It is often used when
> +        the ADC is the only device on the bus. In this mode, SDI is tied to VIO,
> +        and the CNV line can be connected to the CS line of the SPI controller
> +        or to a GPIO, in which case the CS line of the controller is unused.

We have a standard property for this.

> +      * multi: The datasheet calls this "4-wire mode". This is the convential
> +        SPI mode used when there are multiple devices on the same bus. In this
> +        mode, the CNV line is used to initiate the conversion and the SDI line
> +        is connected to CS on the SPI controller.

That's "normal" mode.

> +      * chain: The datasheet calls this "chain mode". This mode is used to save
> +        on wiring when multiple ADCs are used. In this mode, the SDI line of
> +        one chip is tied to the SDO of the next chip in the chain and the SDI of
> +        the last chip in the chain is tied to GND. Only the first chip in the
> +        chain is connected to the SPI bus. The CNV line of all chips are tied
> +        together. The CS line of the SPI controller is unused.

Don't you need to know how many chips are chained? In any case, you just 
need a property for chain mode. There's some existing properties for 
chained devices I think. Standard logic shift register based GPIO IIRC.

CNV are tied together, but must be driven by something? I suppose 
cnv-gpios? But wouldn't that be the same as the SPI controller GPIO CS? 
Does a SPI controller CS line connected to CNV not work in this case?

Rob