Re: [PATCH 4/8] drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()

From: Matt Roper <matthew.d.roper@intel.com>
To: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: <intel-gfx@lists.freedesktop.org>,
	<intel-xe@lists.freedesktop.org>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	<vinod.govindapillai@intel.com>, <stanislav.lisovskiy@intel.com>
Subject: Re: [PATCH 4/8] drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
Date: Mon, 4 Mar 2024 14:11:37 -0800	[thread overview]
Message-ID: <20240304221137.GU5347@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20240304183028.195057-5-gustavo.sousa@intel.com>

On Mon, Mar 04, 2024 at 03:30:23PM -0300, Gustavo Sousa wrote:
> As of Xe2LPD, it is now possible to select the source of the MDCLK
> as either the CD2XCLK or the CDCLK PLL.
> 
> Previous display IPs were hardcoded to use the CD2XCLK. For those, the
> ratio between MDCLK and CDCLK remained constant, namely 2. For Xe2LPD,
> when we select the CDCLK PLL as the source, the ratio will vary
> according to the squashing configuration (since the cd2x divisor is
> fixed for all supported configurations).
> 
> To help the transition to supporting changes in the ratio, extract the
> function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic
> and call it using 2 as hardcoded ratio. Upcoming changes will use that
> function for updates in the ratio due to CDCLK changes.
> 
> Bspec: 50057, 69445, 49213, 68868
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 30 +++++++++++++-------
>  1 file changed, 19 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index c6b9be80d83c..d9e49cd60d3a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3530,6 +3530,21 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>  	return 0;
>  }
>  
> +static void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
> +						u8 ratio,
> +						bool joined_mbus)
> +{
> +	enum dbuf_slice slice;
> +
> +	if (joined_mbus)
> +		ratio *= 2;
> +
> +	for_each_dbuf_slice(i915, slice)
> +		intel_de_rmw(i915, DBUF_CTL_S(slice),
> +			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> +}
> +
>  /*
>   * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
>   * update the request state of all DBUS slices.
> @@ -3537,8 +3552,7 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>  static void update_mbus_pre_enable(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	u32 mbus_ctl, dbuf_min_tracker_val;
> -	enum dbuf_slice slice;
> +	u32 mbus_ctl;
>  	const struct intel_dbuf_state *dbuf_state =
>  		intel_atomic_get_new_dbuf_state(state);
>  
> @@ -3549,24 +3563,18 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
>  	 * TODO: Implement vblank synchronized MBUS joining changes.
>  	 * Must be properly coordinated with dbuf reprogramming.
>  	 */
> -	if (dbuf_state->joined_mbus) {
> +	if (dbuf_state->joined_mbus)
>  		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
>  			MBUS_JOIN_PIPE_SELECT_NONE;
> -		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
> -	} else {
> +	else
>  		mbus_ctl = MBUS_HASHING_MODE_2x2 |
>  			MBUS_JOIN_PIPE_SELECT_NONE;
> -		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
> -	}
>  
>  	intel_de_rmw(i915, MBUS_CTL,
>  		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>  		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
>  
> -	for_each_dbuf_slice(i915, slice)
> -		intel_de_rmw(i915, DBUF_CTL_S(slice),
> -			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> -			     dbuf_min_tracker_val);
> +	intel_dbuf_mdclk_cdclk_ratio_update(i915, 2, dbuf_state->joined_mbus);
>  }
>  
>  void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> -- 
> 2.44.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation