Re: [PATCH v7] xen: Expose the PMU to the guests

From: Ian Jackson <iwj@xenproject.org>
To: Michal Orzel <michal.orzel@arm.com>
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	George Dunlap <george.dunlap@citrix.com>,
	Jan Beulich <jbeulich@suse.com>, Julien Grall <julien@xen.org>,
	Stefano Stabellini <sstabellini@kernel.org>, Wei Liu <wl@xen.org>,
	Nick Rosbrook <rosbrookn@ainfosec.com>,
	Anthony PERARD <anthony.perard@citrix.com>,
	Juergen Gross <jgross@suse.com>,
	Christian Lindig <christian.lindig@citrix.com>,
	David Scott <dave@recoil.org>,
	Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
	bertrand.marquis@arm.com
Subject: Re: [PATCH v7] xen: Expose the PMU to the guests
Date: Wed, 13 Oct 2021 13:49:27 +0100	[thread overview]
Message-ID: <24934.54743.853232.853726@mariner.uk.xensource.com> (raw)
In-Reply-To: <20211013123352.6625-1-michal.orzel@arm.com>

Michal Orzel writes ("[PATCH v7] xen: Expose the PMU to the guests"):
> Add parameter vpmu to xl domain configuration syntax
> to enable the access to PMU registers by disabling
> the PMU traps(currently only for ARM).
> 
> The current status is that the PMU registers are not
> virtualized and the physical registers are directly
> accessible when this parameter is enabled. There is no
> interrupt support and Xen will not save/restore the
> register values on context switches.
> 
> According to Arm Arm, section D7.1:
> "The Performance Monitors Extension is common
> to AArch64 operation and AArch32 operation."
> That means we have an ensurance that if PMU is
> present in one exception state, it must also be
> present in the other.
> 
> Please note that this feature is experimental.
...
> Changes since v6:
> -fix missing "HVM" for vPMU entry in SUPPORT.md

The SUPPORT.md changes LGTM, thanks.

> -Virtual Performance Management Unit for HVM guests
> +Virtual Performance Management Unit
>  
> -    Status, x86: Supported, Not security supported
> +    Status, x86 HVM: Supported, Not security supported
> +    Status, ARM: Experimental
> +
> +On ARM, support for accessing PMU registers from the guests.
> +There is no interrupt support and Xen will not save/restore
> +the register values on context switches.

FTAOD ISTM that this limitation makes the feature very hard to use
successfully on ARM.  You would need to pin vcpus to dedicated
pcpus ?

I think this is fine for an experimental feature.

I think this patch needs a ARM/hypervisor acks still.

Ian.