From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn, palmer@rivosinc.com
Subject: Re: [PATCH for-8.1 v3 03/26] target/riscv/cpu.c: remove set_priv_version()
Date: Tue, 21 Mar 2023 09:50:25 +0800 [thread overview]
Message-ID: <2e945bcf-831f-4313-7b8d-d2091f0d8076@linux.alibaba.com> (raw)
In-Reply-To: <20230318200436.299464-4-dbarboza@ventanamicro.com>
On 2023/3/19 4:04, Daniel Henrique Barboza wrote:
> The setter is doing nothing special. Just set env->priv_ver directly.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 30 +++++++++++++-----------------
> 1 file changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2752efe1eb..18032dfd4e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -240,11 +240,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> env->misa_ext_mask = env->misa_ext = ext;
> }
>
> -static void set_priv_version(CPURISCVState *env, int priv_ver)
> -{
> - env->priv_ver = priv_ver;
> -}
> -
> #ifndef CONFIG_USER_ONLY
> static uint8_t satp_mode_from_str(const char *satp_mode_str)
> {
> @@ -343,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj)
> VM_1_10_SV32 : VM_1_10_SV57);
> #endif
>
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> register_cpu_props(obj);
> }
>
> @@ -355,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj)
> set_misa(env, MXL_RV64, 0);
> register_cpu_props(obj);
> /* Set latest version of privileged specification */
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> #endif
> @@ -366,7 +361,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> register_cpu_props(obj);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> #endif
> @@ -379,7 +374,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> register_cpu_props(obj);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -392,7 +387,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_11_0);
> + env->priv_ver = PRIV_VERSION_1_11_0;
>
> cpu->cfg.ext_g = true;
> cpu->cfg.ext_c = true;
> @@ -431,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj)
> set_misa(env, MXL_RV128, 0);
> register_cpu_props(obj);
> /* Set latest version of privileged specification */
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> #endif
> @@ -444,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj)
> set_misa(env, MXL_RV32, 0);
> register_cpu_props(obj);
> /* Set latest version of privileged specification */
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> #endif
> @@ -454,8 +449,9 @@ static void rv32_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +
> register_cpu_props(obj);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> #endif
> @@ -468,7 +464,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> register_cpu_props(obj);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -482,7 +478,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>
> set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> register_cpu_props(obj);
> - set_priv_version(env, PRIV_VERSION_1_11_0);
> + env->priv_ver = PRIV_VERSION_1_11_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -497,7 +493,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> register_cpu_props(obj);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -1160,7 +1156,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
>
> if (priv_version >= PRIV_VERSION_1_10_0) {
> - set_priv_version(env, priv_version);
> + env->priv_ver = priv_version;
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> }
>
> /* Force disable extensions if priv spec version does not match */
next prev parent reply other threads:[~2023-03-21 1:50 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-18 20:04 [PATCH for-8.1 v3 00/26] target/riscv: rework CPU extensions validation Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 01/26] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-03-21 1:47 ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 02/26] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-03-21 1:49 ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 03/26] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-03-21 1:50 ` LIU Zhiwei [this message]
2023-03-18 20:04 ` [PATCH for-8.1 v3 04/26] target/riscv: add PRIV_VERSION_LATEST Daniel Henrique Barboza
2023-03-21 1:50 ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Daniel Henrique Barboza
2023-03-21 4:51 ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 11/26] target/riscv/cpu.c: set cpu config in set_misa() Daniel Henrique Barboza
2023-03-21 3:54 ` liweiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 12/26] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 14/26] target/riscv: add RVG Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions() Daniel Henrique Barboza
2023-03-21 3:10 ` liweiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 16/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 17/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 18/26] target/riscv: error out on priv failure for RVH Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 19/26] target/riscv: write env->misa_ext* in register_generic_cpu_props() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 20/26] target/riscv: make validate_misa_ext() use a misa_ext val Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 21/26] target/riscv: split riscv_cpu_validate_set_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 23/26] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 24/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 25/26] target/riscv: allow write_misa() to enable RVG Daniel Henrique Barboza
2023-03-21 3:25 ` liweiwei
2023-03-22 17:42 ` Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 26/26] target/riscv: allow write_misa() to enable RVV Daniel Henrique Barboza
2023-03-21 3:41 ` liweiwei
2023-03-22 17:39 ` Daniel Henrique Barboza
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