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From: "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 08/12] drm/i915: Simplify intel_get_crtc_ycbcr_config()
Date: Wed, 18 Sep 2019 19:02:22 +0000	[thread overview]
Message-ID: <301f150fb57070860f7bdf9401e9740be66e1386.camel@intel.com> (raw)
In-Reply-To: <20190718145053.25808-9-ville.syrjala@linux.intel.com>

On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make intel_get_crtc_ycbcr_config() simpler and rename it
> to bdw_get_pipemisc_output_format() to better reflect what
> it does.
> 
> Also toss in some comments to document that the 4:2:0 PIPECONF
> bits are glk+ only. They are mbz on earlier platforms so reading
> them unconditionally is safe however.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 71 +++++++++---------
> --
>  drivers/gpu/drm/i915/i915_reg.h              |  4 +-
>  2 files changed, 34 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ffdc350dc24a..1dd1aa29a649 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8713,47 +8713,24 @@ static void chv_crtc_clock_get(struct
> intel_crtc *crtc,
>  	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
>  }
>  
> -static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
> -					struct intel_crtc_state
> *pipe_config)
> +static enum intel_output_format
> +bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
> -
> -	pipe_config->lspcon_downsampling = false;
> -
> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
> -		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
> -
> -		if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
> -			bool ycbcr420_enabled = tmp &
> PIPEMISC_YUV420_ENABLE;
> -			bool blend = tmp &
> PIPEMISC_YUV420_MODE_FULL_BLEND;
> -
> -			if (ycbcr420_enabled) {
> -				/* We support 4:2:0 in full blend mode
> only */
> -				if (!blend)
> -					output =
> INTEL_OUTPUT_FORMAT_INVALID;
> -				else if (!(IS_GEMINILAKE(dev_priv) ||
> -					   INTEL_GEN(dev_priv) >= 10))
> -					output =
> INTEL_OUTPUT_FORMAT_INVALID;
> -				else
> -					output =
> INTEL_OUTPUT_FORMAT_YCBCR420;
> -			} else {
> -				/*
> -				 * Currently there is no interface
> defined to
> -				 * check user preference between
> RGB/YCBCR444
> -				 * or YCBCR420. So the only possible
> case for
> -				 * YCBCR444 usage is driving YCBCR420
> output
> -				 * with LSPCON, when pipe is configured
> for
> -				 * YCBCR444 output and LSPCON takes
> care of
> -				 * downsampling it.
> -				 */
> -				pipe_config->lspcon_downsampling =
> true;
> -				output = INTEL_OUTPUT_FORMAT_YCBCR444;
> -			}
> -		}
> -	}
> +	u32 tmp;
> +
> +	tmp = I915_READ(PIPEMISC(crtc->pipe));
>  
> -	pipe_config->output_format = output;
> +	if (tmp & PIPEMISC_YUV420_ENABLE) {
> +		/* We support 4:2:0 in full blend mode only */
> +		WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
> +
> +		return INTEL_OUTPUT_FORMAT_YCBCR420;
> +	} else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
> +		return INTEL_OUTPUT_FORMAT_YCBCR444;
> +	} else {
> +		return INTEL_OUTPUT_FORMAT_RGB;
> +	}
>  }
>  
>  static void i9xx_get_pipe_color_config(struct intel_crtc_state
> *crtc_state)
> @@ -10445,7 +10422,23 @@ static bool haswell_get_pipe_config(struct
> intel_crtc *crtc,
>  	}
>  
>  	intel_get_pipe_src_size(crtc, pipe_config);
> -	intel_get_crtc_ycbcr_config(crtc, pipe_config);
> +
> +	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
> +		pipe_config->output_format =
> +			bdw_get_pipemisc_output_format(crtc);
> +
> +		/*
> +		 * Currently there is no interface defined to
> +		 * check user preference between RGB/YCBCR444
> +		 * or YCBCR420. So the only possible case for
> +		 * YCBCR444 usage is driving YCBCR420 output
> +		 * with LSPCON, when pipe is configured for
> +		 * YCBCR444 output and LSPCON takes care of
> +		 * downsampling it.
> +		 */
> +		pipe_config->lspcon_downsampling =
> +			pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +	}
>  
>  	pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 91bf714897e5..66f7f417231f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5803,8 +5803,8 @@ enum {
>  
>  #define _PIPE_MISC_A			0x70030
>  #define _PIPE_MISC_B			0x71030
> -#define   PIPEMISC_YUV420_ENABLE	(1 << 27)
> -#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
> +#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
> +#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
>  #define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
>  #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
>  #define   PIPEMISC_DITHER_BPC_MASK	(7 << 5)
The changes look good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2019-09-18 19:02 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-18 14:50 [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjala
2019-07-18 14:50 ` [PATCH 01/12] drm/dp: Add definitons for MSA MISC bits Ville Syrjala
2019-09-18 18:55   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 02/12] drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication Ville Syrjala
2019-09-18 18:59   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 03/12] drm/i915: Fix AVI infoframe quantization range for YCbCr output Ville Syrjala
2019-09-20 12:56   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 04/12] drm/i915: Extract intel_hdmi_limited_color_range() Ville Syrjala
2019-09-18 19:00   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 05/12] drm/i915: Never set limited_color_range=true for YCbCr output Ville Syrjala
2019-07-18 16:45   ` [PATCH v2 " Ville Syrjala
2019-09-18 19:01     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 06/12] drm/i915: Switch to using DP_MSA_MISC_* defines Ville Syrjala
2019-09-18 19:01   ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 07/12] drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout Ville Syrjala
2019-09-18 19:02   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 08/12] drm/i915: Simplify intel_get_crtc_ycbcr_config() Ville Syrjala
2019-09-18 19:02   ` Mun, Gwan-gyeong [this message]
2019-07-18 14:50 ` [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW Ville Syrjala
2019-09-18 19:03   ` Mun, Gwan-gyeong
2019-09-20 12:20     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 10/12] drm/i915: Document ILK+ pipe csc matrix better Ville Syrjala
2019-09-20 14:24   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-09-20 14:29     ` Ville Syrjälä
2019-07-18 14:50 ` [PATCH 11/12] drm/i915: Set up ILK/SNB csc unit properly for YCbCr output Ville Syrjala
2019-09-20 12:19   ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB Ville Syrjala
2019-09-18 19:05   ` Mun, Gwan-gyeong
2019-09-20 12:21     ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 15:33 ` ✗ Fi.CI.BAT: failure for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Patchwork
2019-07-18 17:21 ` ✓ Fi.CI.BAT: success for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output (rev2) Patchwork
2019-07-18 20:11 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-20 18:48 ` [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjälä

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