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From: Michal Simek <michal.simek@amd.com>
To: Tom Rini <trini@konsulko.com>
Cc: <u-boot@lists.denx.de>, <git@xilinx.com>,
	Christian Kohn <christian.kohn@xilinx.com>,
	Michal Simek <monstr@monstr.eu>
Subject: Re: [PATCH] ARM: zynq: DT: Enable all FCLKs by default
Date: Thu, 7 Jul 2022 14:39:27 +0200	[thread overview]
Message-ID: <30d0415a-2776-5213-6f6b-d7337ff8f88d@amd.com> (raw)
In-Reply-To: <20220707123119.GP1146598@bill-the-cat>

Hi Tom,

On 7/7/22 14:31, Tom Rini wrote:
> On Thu, Jul 07, 2022 at 12:50:10PM +0200, Michal Simek wrote:
> 
>> From: Christian Kohn <christian.kohn@xilinx.com>
>>
>> The fclk-enable property is set to 0 which disables all FCLKs.
>> Enable all FCLKs so they can be used as clock sources in the
>> programmable logic.
>>
>> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>> ---
>>
>>   arch/arm/dts/zynq-7000.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Since this (and the other patch today) are touching a common dtsi file,
> what is the status of these changes with upstream?  Thanks.

Versal reset DT header is in Linux kernel already
mmio-sram is enabled for zc702 board in kernel already but it is generic for all.
#stream-id-cells - already removed in the kernel

And this fclk not sent to upstream linux yet.

Thanks,
Michal

  reply	other threads:[~2022-07-07 12:39 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-07 10:50 [PATCH] ARM: zynq: DT: Enable all FCLKs by default Michal Simek
2022-07-07 12:31 ` Tom Rini
2022-07-07 12:39   ` Michal Simek [this message]
2022-10-12  9:30 Michal Simek
2022-10-25  8:29 ` Michal Simek

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