Re: [PATCH] target/xtensa: fix access ring in l32ex - Philippe Mathieu-Daudé

From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Max Filippov <jcmvbkbc@gmail.com>, qemu-devel@nongnu.org
Cc: Joaquin de Andres <me@xcancerberox.com.ar>, qemu-stable@nongnu.org
Subject: Re: [PATCH] target/xtensa: fix access ring in l32ex
Date: Wed, 19 May 2021 15:56:19 +0200	[thread overview]
Message-ID: <3811d64f-b41e-c73a-05f9-4fec714e128e@amsat.org> (raw)
In-Reply-To: <20210519104433.16870-1-jcmvbkbc@gmail.com>

Cc'ing Joaquin who has interest in Xtensa ISA :)

On 5/19/21 12:44 PM, Max Filippov wrote:
> l32ex does memory access as all regular load/store operations at CRING
> level. Fix apparent pasto from l32e that caused it to use RING instead.
> 
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
>  target/xtensa/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
> index f93df87ec490..95f6b21c2a1e 100644
> --- a/target/xtensa/translate.c
> +++ b/target/xtensa/translate.c
> @@ -1814,7 +1814,7 @@ static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[],
>      tcg_gen_mov_i32(addr, arg[1].in);
>      gen_load_store_alignment(dc, 2, addr, true);
>      gen_check_exclusive(dc, addr, false);
> -    tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->ring, MO_TEUL);
> +    tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, MO_TEUL);
>      tcg_gen_mov_i32(cpu_exclusive_addr, addr);
>      tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out);
>      tcg_temp_free(addr);
> 

Looking at s32ex, it makes sense.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>