From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Pu Wen <puwen@hygon.cn>, <xen-devel@lists.xenproject.org>
Cc: "Wei Liu" <wei.liu2@citrix.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [Xen-devel] [PATCH v6] x86/pv: Add Hygon Dhyana support to emulate MSRs access
Date: Wed, 12 Jun 2019 14:03:18 +0100 [thread overview]
Message-ID: <40b0052d-6077-9e6f-ed6e-0e5db88a2559@citrix.com> (raw)
In-Reply-To: <86038466e1e7a77449230f97e19e9c3f436fd029.1560342915.git.puwen@hygon.cn>
On 12/06/2019 13:54, Pu Wen wrote:
> The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
> counter MSRs, hardware configuration MSR, MMIO configuration base address
> MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
> PV emulation infrastructure by using the code path of AMD.
>
> [Rebase over 0cd07414 "x86/cpu: Renumber X86_VENDOR_* to form a bitmap"]
>
> Signed-off-by: Pu Wen <puwen@hygon.cn>
> Acked-by: Jan Beulich <jbeulich@suse.com>
Thanks. I'll commit both of these patches in due course.
~Andrew
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prev parent reply other threads:[~2019-06-12 13:03 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-12 12:54 [Xen-devel] [PATCH v6] x86/pv: Add Hygon Dhyana support to emulate MSRs access Pu Wen
2019-06-12 13:03 ` Andrew Cooper [this message]
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