Re: [PATCH 05/11] drm/i915/execlists: Process one CSB interrupt at a time

From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/11] drm/i915/execlists: Process one CSB interrupt at a time
Date: Tue, 5 Jun 2018 09:30:06 +0100	[thread overview]
Message-ID: <4203cc39-3efc-441f-287d-2ccc482057a2@linux.intel.com> (raw)
In-Reply-To: <152812633633.7032.10930408782379104398@mail.alporthouse.com>

On 04/06/2018 16:32, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-06-04 15:27:34)
>>
>> On 31/05/2018 19:51, Chris Wilson wrote:
>>> In the next patch, we will process the CSB events directly from the CS
>>> interrupt handler, being called for each interrupt. Hence, we will no
>>
>> Correct to explain it is the user interrupt handler.
> 
> ?

Series is not processing CSB from the CS interrupt, but from the user 
interrupt handler, via notify ring, fence signal, etc, as discussed in 
the other sub-thread. Or I am still missing something?

>>> longer have the need for a loop until the has-interrupt bit is clear,
>>> and in the meantime can remove that small optimisation.
>>
>> Hm, isn't this assuming the optimistic csb processing from user
>> interrupt sees the event? If it doesn't, couldn't we still end up
>> needing the loop here?
> 
> No. We get the CS interrupt when hw updates the write pointer. (Not sure
> if it's just the first write.)

Yeah I confused something here.

Regards,

Tvrtko

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