From: Ludwig Petrosyan <ludwig.petrosyan@desy.de>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Jonathan Corbet <corbet@lwn.net>,
Rob Herring <robh+dt@kernel.org>, Jon Mason <jdmason@kudzu.us>,
Dave Jiang <dave.jiang@intel.com>,
Allen Hubbe <allenbh@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
linux-pci@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-ntb@googlegroups.com
Subject: Re: [RFC PATCH 19/21] PCI: Add TI J721E device to pci ids
Date: Thu, 26 Sep 2019 13:45:27 +0200 [thread overview]
Message-ID: <4832a387-c18a-8c04-98a0-cfc46db09243@desy.de> (raw)
In-Reply-To: <20190926112933.8922-20-kishon@ti.com>
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Dear Linux kernel group
We are using MTCA systems with Ubuntu Linux and PCIe as a central bus
We got some problem:
some times the memories of the PCIe endpoints not mapped and the lspci
gives strange otput:
uname -a : Linux mcscpudev6 4.15.0-45-generic #48~16.04.1-Ubuntu SMP Tue
Jan 29 18:03:48 UTC 2019 x86_64 x86_64 x86_64 GNU/Linux
/lspci -vvvv -s 05:00.0//
//05:00.0 Signal processing controller: Xilinx Corporation Device 0088//
// Subsystem: Device 3300:0088//
// Physical Slot: 4//
// Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+//
// Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-//
// Latency: 0, Cache Line Size: 64 bytes//
// Interrupt: pin A routed to IRQ 223//
//_Region 0: Memory at <ignored> (32-bit, non-prefetchable)_/_/
/__/ Region 1: Memory at <ignored> (32-bit, non-prefetchable)/__/
/__/ Region 2: Memory at <ignored> (32-bit, non-prefetchable)/_/
// Expansion ROM at 71c00000 [disabled] [size=1M]//
// Capabilities: [40] Power Management version 3//
// Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)//
// Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-//
// Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+//
// Address: 00000000fee00ef8 Data: 0000//
// Capabilities: [60] Express (v1) Endpoint, MSI 00//
// DevCap: MaxPayload 512 bytes, PhantFunc 1, Latency L0s
unlimited, L1 unlimited//
// ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-//
// DevCtl: Report errors: Correctable- Non-Fatal- Fatal-
Unsupported-//
// RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+//
// MaxPayload 256 bytes, MaxReadReq 512 bytes//
// DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr-
TransPend-//
// LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit
Latency L0s unlimited, L1 unlimited//
// ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-//
// LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-//
// ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-//
// LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+
DLActive- BWMgmt- ABWMgmt-//
// Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00//
// Kernel driver in use: pciedev//
// Kernel modules: pciedev//
/
but lspci with -H1:
/lspci -H1 -vvvv -s 05:00.0//
//05:00.0 Signal processing controller: Xilinx Corporation Device 0088//
// Subsystem: Device 3300:0088//
// Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+//
// Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-//
// Latency: 0, Cache Line Size: 64 bytes//
// Interrupt: pin A routed to IRQ 10//
////_Region 0: Memory at d8000000 (32-bit, non-prefetchable)_//_
_//_ Region 1: Memory at d4000000 (32-bit, non-prefetchable)_//_
_//_ Region 2: Memory at dc000000 (32-bit, non-prefetchable)_//
// Expansion ROM at dd000000 [disabled]//
// Capabilities: [40] Power Management version 3//
// Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)//
// Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-//
// Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+//
// Address: 00000000fee00ef8 Data: 0000//
// Capabilities: [60] Express (v1) Endpoint, MSI 00//
// DevCap: MaxPayload 512 bytes, PhantFunc 1, Latency L0s
unlimited, L1 unlimited//
// ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-//
// DevCtl: Report errors: Correctable- Non-Fatal- Fatal-
Unsupported-//
// RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+//
// MaxPayload 256 bytes, MaxReadReq 512 bytes//
// DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr-
TransPend-//
// LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Exit
Latency L0s unlimited, L1 unlimited//
// ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-//
// LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-//
// ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-//
// LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+
DLActive- BWMgmt- ABWMgmt-/
adding pci=realloc=off solves with problem.
Is it in general a good idea to use "pci=realloc=off"?
And what the problem? Would some body so kinde to explane what the problem?!
with best regards
Ludwig Petrosyan
On 9/26/19 1:29 PM, Kishon Vijay Abraham I wrote:
> Add TI J721E device to the pci id database. Since this device has
> a configurable PCIe endpoint, it could be used with different
> drivers.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> include/linux/pci_ids.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index d157983b84cf..b2820a834a5e 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -868,6 +868,7 @@
> #define PCI_DEVICE_ID_TI_X620 0xac8d
> #define PCI_DEVICE_ID_TI_X420 0xac8e
> #define PCI_DEVICE_ID_TI_XX20_FM 0xac8f
> +#define PCI_DEVICE_ID_TI_J721E 0xb00d
> #define PCI_DEVICE_ID_TI_DRA74x 0xb500
> #define PCI_DEVICE_ID_TI_DRA72x 0xb501
>
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next prev parent reply other threads:[~2019-09-26 11:45 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 11:29 [RFC PATCH 00/21] Implement NTB Controller using multiple PCI Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 01/21] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF Bus Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 02/21] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF Device Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-10-15 18:42 ` Rob Herring
2019-10-16 4:45 ` Kishon Vijay Abraham I
2019-10-16 4:45 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 03/21] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF NTB Device Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 04/21] Documentation: PCI: Add specification for the *PCI NTB* function device Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-11-17 23:26 ` Jon Mason
2019-09-26 11:29 ` [RFC PATCH 05/21] PCI: endpoint: Add API to get reference to EPC from device-tree Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-11-17 23:28 ` Jon Mason
2019-09-26 11:29 ` [RFC PATCH 06/21] PCI: endpoint: Add API to create EPF device from device tree Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 07/21] PCI: endpoint: Add "pci-epf-bus" driver Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 08/21] PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 09/21] PCI: endpoint: Add helper API to get the 'next' unreserved BAR Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 10/21] PCI: endpoint: Make pci_epf_driver ops optional Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 11/21] PCI: endpoint: Add helper API to populate header with values from DT Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 12/21] PCI: endpoint: Add support to associate secondary EPC with EPF Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 13/21] PCI: endpoint: Add pci_epc_ops to map MSI irq Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 14/21] PCI: cadence: Implement ->msi_map_irq() ops Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 15/21] PCI: endpoint: Remove unused pci_epf_match_device() Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 16/21] PCI: endpoint: Fix missing mutex_unlock in error case Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 17/21] PCI: endpoint: *_free_bar() to return error codes on failure Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 18/21] PCI: endpoint: Add EP function driver to provide NTB functionality Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:29 ` [RFC PATCH 19/21] PCI: Add TI J721E device to pci ids Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-09-26 11:45 ` Ludwig Petrosyan [this message]
2019-09-26 11:29 ` [RFC PATCH 20/21] NTB: Add support for EPF PCI-Express Non-Transparent Bridge Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-11-17 23:40 ` Jon Mason
2019-09-26 11:29 ` [RFC PATCH 21/21] NTB: tool: Enable the NTB/PCIe link on the local or remote side of bridge Kishon Vijay Abraham I
2019-09-26 11:29 ` Kishon Vijay Abraham I
2019-11-17 23:43 ` [RFC PATCH 00/21] Implement NTB Controller using multiple PCI Jon Mason
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