Re: [PATCH v5 07/11] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation

From: Yi Liu <yi.l.liu@intel.com>
To: Baolu Lu <baolu.lu@linux.intel.com>, <joro@8bytes.org>,
	<alex.williamson@redhat.com>, <jgg@nvidia.com>,
	<kevin.tian@intel.com>, <robin.murphy@arm.com>
Cc: <cohuck@redhat.com>, <eric.auger@redhat.com>,
	<nicolinc@nvidia.com>, <kvm@vger.kernel.org>,
	<mjrosato@linux.ibm.com>, <chao.p.peng@linux.intel.com>,
	<yi.y.sun@linux.intel.com>, <peterx@redhat.com>,
	<jasowang@redhat.com>, <shameerali.kolothum.thodi@huawei.com>,
	<lulu@redhat.com>, <suravee.suthikulpanit@amd.com>,
	<iommu@lists.linux.dev>, <linux-kernel@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>, <zhenzhong.duan@intel.com>,
	<joao.m.martins@oracle.com>
Subject: Re: [PATCH v5 07/11] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation
Date: Mon, 25 Sep 2023 14:56:45 +0800	[thread overview]
Message-ID: <49bd7209-27f0-4bac-59bb-5a59fb21f872@intel.com> (raw)
In-Reply-To: <e493c62d-8f10-17c8-f660-dbae19c481a4@linux.intel.com>

On 2023/9/21 21:33, Baolu Lu wrote:
> On 2023/9/21 15:54, Yi Liu wrote:
>> This adds the data structure for flushing iotlb for the nested domain
>> allocated with IOMMU_HWPT_TYPE_VTD_S1 type.
>>
>> This only supports invalidating IOTLB, but no for device-TLB as device-TLB
>> invalidation will be covered automatically in the IOTLB invalidation if the
>> underlying IOMMU driver has enabled ATS for the affected device.
>>
>> Signed-off-by: Yi Liu <yi.l.liu@intel.com>
>> ---
>>   include/uapi/linux/iommufd.h | 34 ++++++++++++++++++++++++++++++++++
>>   1 file changed, 34 insertions(+)
>>
>> diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h
>> index 18a502e206c3..3050efbceb57 100644
>> --- a/include/uapi/linux/iommufd.h
>> +++ b/include/uapi/linux/iommufd.h
>> @@ -510,6 +510,40 @@ struct iommu_hw_info {
>>   };
>>   #define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO)
>> +/**
>> + * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
>> + *                                           stage-1 cache invalidation
>> + * @IOMMU_VTD_QI_FLAGS_LEAF: The LEAF flag indicates whether only the
>> + *                           leaf PTE caching needs to be invalidated
>> + *                           and other paging structure caches can be
>> + *                           preserved.
>> + */
>> +enum iommu_hwpt_vtd_s1_invalidate_flags {
>> +    IOMMU_VTD_QI_FLAGS_LEAF = 1 << 0,
>> +};
>> +
>> +/**
>> + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
>> + *                                       (IOMMU_HWPT_TYPE_VTD_S1)
>> + * @addr: The start address of the addresses to be invalidated.
> 
> Is there an alignment requirement for @addr? If so, is 4K alignment
> sufficient? Perhaps we need to document it here so that user space can
> calculate the @addr correctly.

yes, it should be aligned. let's document it in the kdoc.

> 
>> + * @npages: Number of contiguous 4K pages to be invalidated.
>> + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
>> + * @__reserved: Must be 0
>> + *
>> + * The Intel VT-d specific invalidation data for user-managed stage-1 cache
>> + * invalidation under nested translation. Userspace uses this structure to
>> + * tell host about the impacted caches after modifying the stage-1 page 
>> table.
>> + *
>> + * Invalidating all the caches related to the page table by setting @addr
>> + * to be 0 and @npages to be __aligned_u64(-1).
>> + */
>> +struct iommu_hwpt_vtd_s1_invalidate {
>> +    __aligned_u64 addr;
>> +    __aligned_u64 npages;
>> +    __u32 flags;
>> +    __u32 __reserved;
>> +};
>> +
>>   /**
>>    * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
>>    * @size: sizeof(struct iommu_hwpt_invalidate)
> 
> Best regards,
> baolu

-- 
Regards,
Yi Liu