From: ashwinc@codeaurora.org (Ashwin Chaugule)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 10/10] ARM: perf: add mode exclusion for Cortex-A15 PMU
Date: Wed, 24 Aug 2011 23:09:13 -0400 [thread overview]
Message-ID: <4E55BCD9.7050703@codeaurora.org> (raw)
In-Reply-To: <CAKHPGBZ1eXzhsjFvLt_KTYKsR_OH7rgbeSGedTY5g8dhi90uzQ@mail.gmail.com>
Hey Will,
> From: Will Deacon <will.deacon@arm.com>
>
> The Cortex-A15 PMU implements the PMUv2 specification and therefore
> has support for some mode exclusion.
>
> This patch adds support for excluding user, kernel and hypervisor counts
> from a given event.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
--8<---
> +
> +/*
> + * Event filters for PMUv2
> + */
> +#define ARMV7_EXCLUDE_PL1 (1 << 31)
> +#define ARMV7_EXCLUDE_USER (1 << 30)
> +#define ARMV7_INCLUDE_HYP (1 << 27)
> +
This mode exclusion stuff is confusing me.
For exclude user mode, shouldn't PMXEVTYPER[PL1,U] = 0b11
With this patch the counters will spin with secure mode activity as well,
if exclude user mode is selected ?
/me goes to bother the h/w guys.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-08-25 3:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-08 17:16 [PATCH 00/10] ARM: perf: updates for 3.2 Will Deacon
2011-08-08 17:16 ` [PATCH 01/10] ARM: perf: de-const struct arm_pmu Will Deacon
2011-08-08 17:16 ` [PATCH 02/10] ARM: PMU: move CPU PMU platform device handling and init into perf Will Deacon
2011-08-08 17:16 ` [PATCH 03/10] ARM: perf: use cpumask_t to record active IRQs Will Deacon
2011-08-08 17:16 ` [PATCH 04/10] ARM: perf: use u32 instead of unsigned long for PMNC register Will Deacon
2011-08-08 17:16 ` [PATCH 05/10] ARM: perf: use integers for ARMv7 event indices Will Deacon
2011-08-08 17:16 ` [PATCH 06/10] ARM: perf: index ARMv7 event counters starting from zero Will Deacon
2011-08-08 17:16 ` [PATCH 07/10] ARM: perf: index Xscale and ARMv6 " Will Deacon
2011-08-08 17:16 ` [PATCH 08/10] ARM: perf: index PMU registers " Will Deacon
2011-08-08 17:16 ` [PATCH 09/10] ARM: perf: allow armpmu to implement mode exclusion Will Deacon
2011-08-08 17:16 ` [PATCH 10/10] ARM: perf: add mode exclusion for Cortex-A15 PMU Will Deacon
[not found] ` <CAKHPGBZ1eXzhsjFvLt_KTYKsR_OH7rgbeSGedTY5g8dhi90uzQ@mail.gmail.com>
2011-08-25 3:09 ` Ashwin Chaugule [this message]
2011-08-25 9:51 ` Will Deacon
2011-08-09 9:35 ` [PATCH 00/10] ARM: perf: updates for 3.2 Jamie Iles
2011-08-09 9:42 ` Will Deacon
2011-08-09 9:54 ` Jamie Iles
2011-08-09 10:01 ` Will Deacon
2011-08-09 10:14 ` Jean Pihet
2011-08-09 10:52 ` Will Deacon
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