[Qemu-devel] [PULL 05/11] target/openrisc: add numcores and coreid support

From: Stafford Horne <shorne@gmail.com>
To: peter.maydell@linaro.org
Cc: QEMU Development <qemu-devel@nongnu.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PULL 05/11] target/openrisc: add numcores and coreid support
Date: Mon,  1 May 2017 08:14:19 +0900	[thread overview]
Message-ID: <4d3ebb3092f5ac66a58357cee15bd5432e77f2fe.1493593744.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1493593744.git.shorne@gmail.com>
In-Reply-To: <cover.1493593744.git.shorne@gmail.com>

These are used to identify the processor in SMP system.  Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.

The proposal for this is available:
  https://openrisc.io/proposals/core-identifier-and-number-of-cores

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/sys_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 6ba8162..e13666b 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 64): /* ESR */
         return env->esr;
 
+    case TO_SPR(0, 128): /* COREID */
+        return 0;
+
+    case TO_SPR(0, 129): /* NUMCORES */
+        return 1;
+
     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
         idx = spr - TO_SPR(1, 512);
         return env->tlb->dtlb[0][idx].mr;
-- 
2.9.3
