Re: [PATCH] spi: stm32: FIFO threshold level - fix align packet size

From: Marek Vasut <marex@denx.de>
To: Roman Guskov <rguskov@dh-electronics.com>, linux-spi@vger.kernel.org
Cc: broonie@kernel.org, alexandre.torgue@st.com,
	linux-stm32@st-md-mailman.stormreply.com,
	Amelie DELAUNAY <amelie.delaunay@foss.st.com>
Subject: Re: [PATCH] spi: stm32: FIFO threshold level - fix align packet size
Date: Mon, 21 Dec 2020 13:51:48 +0100	[thread overview]
Message-ID: <524f6c50-b515-1f5e-8237-97e78c9875d8@denx.de> (raw)
In-Reply-To: <20201221123532.27272-1-rguskov@dh-electronics.com>

On 12/21/20 1:35 PM, Roman Guskov wrote:
> if cur_bpw <= 8 and xfer_len < 4 then the value of fthlv will be 1 and
> SPI registers content may have been lost.
> 
> * If SPI data register is accessed as a 16-bit register and DSIZE <= 8bit,
>    better to select FTHLV = 2, 4, 6 etc
> 
> * If SPI data register is accessed as a 32-bit register and DSIZE > 8bit,
>    better to select FTHLV = 2, 4, 6 etc, while if DSIZE <= 8bit,
>    better to select FTHLV = 4, 8, 12 etc
> 
> Signed-off-by: Roman Guskov <rguskov@dh-electronics.com>

I think this should also have the following tag:

Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")

> ---
>   drivers/spi/spi-stm32.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
> index 9d8ceb63f7db..417c40154477 100644
> --- a/drivers/spi/spi-stm32.c
> +++ b/drivers/spi/spi-stm32.c
> @@ -494,9 +494,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
>   
>   	/* align packet size with data registers access */
>   	if (spi->cur_bpw > 8)
> -		fthlv -= (fthlv % 2); /* multiple of 2 */
> +		fthlv += (fthlv % 2) ? 1 : 0;
>   	else
> -		fthlv -= (fthlv % 4); /* multiple of 4 */
> +		fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
>   
>   	if (!fthlv)
>   		fthlv = 1;
> 

Reviewed-by: Marek Vasut <marex@denx.de>