Re: [PATCH] mmc: dw_mmc: add support for RK3288.

From: addy ke <addy.ke@rock-chips.com>
To: jh80.chung@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com,
	mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
	galak@codeaurora.org, rdunlap@infradead.org,
	tgih.jun@samsung.com, chris@printf.net, ulf.hansson@linaro.org,
	dinguyen@altera.com, heiko@sntech.de, olof@lixom.net
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
	hj@rock-chips.com, kever.yang@rock-chips.com, xjq@rock-chips.com,
	huangtao@rock-chips.com, zyw@rock-chips.com, yzq@rock-chips.com,
	zhenfu.fang@rock-chips.com, cf@rock-chips.com,
	zhangqing@rock-chips.com, hl@rock-chips.com,
	lintao@rock-chips.com, chenfen@rock-chips.com,
	zyf@rock-chips.com
Subject: Re: [PATCH] mmc: dw_mmc: add support for RK3288.
Date: Mon, 07 Jul 2014 10:42:18 +0800	[thread overview]
Message-ID: <53BA090A.30509@rock-chips.com> (raw)
In-Reply-To: <53BA00CC.2090707@samsung.com>

> Hi, Addy,
> 
> On 07/05/2014 09:59 PM, addy ke wrote:
>> This patch focuses on clock setting for RK3288 mmc controller.
>>
>> In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
>> and if DDR 8bit mode, CLKDIV register must be set 1.
>>
>> Signed-off-by: addy ke <addy.ke@rock-chips.com>
>> ---
>>  .../devicetree/bindings/mmc/rockchip-dw-mshc.txt   |  4 +-
>>  drivers/mmc/host/dw_mmc-pltfm.c                    | 50 +++++++++++++++++++++-
>>  2 files changed, 51 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
>> index c559f3f..e3f95cd 100644
>> --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
>> @@ -10,7 +10,9 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
>>  Required Properties:
>>  
>>  * compatible: should be
>> -	- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following
>> +	- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
>> +							before RK3288
>> +	- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
>>  
>>  Example:
>>  
>> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
>> index d4a47a9..15d796e 100644
>> --- a/drivers/mmc/host/dw_mmc-pltfm.c
>> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
>> @@ -21,17 +21,61 @@
>>  #include <linux/mmc/mmc.h>
>>  #include <linux/mmc/dw_mmc.h>
>>  #include <linux/of.h>
>> +#include <linux/clk.h>
>>  
>>  #include "dw_mmc.h"
>>  #include "dw_mmc-pltfm.h"
>>  
>> +#define RK3288_CLKGEN_DIV	2
> "2" is used to the general div value at rockchip?
> 
Yes, In RK3288, the div generated by CLKGEN is 2 and can not be changed by software.
>> +
>>  static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr)
>>  {
>>  	*cmdr |= SDMMC_CMD_USE_HOLD_REG;
>>  }
>>  
>> -static const struct dw_mci_drv_data rockchip_drv_data = {
>> +static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
>> +{
>> +	host->bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
> I knew that you need not to call clk_get_rate(). In dw-mmc.c, it's already called.
> So you can just use the host->bus_hz.
> 
> host->bus_hz /= RK3288_CLKGEN_DIV;
> 
> Best Regards,
> Jaehoon Chung
> 
>> +
>> +	return 0;
>> +}
>> +
>> +static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>> +{
>> +	int ret;
>> +	unsigned int cclkin;
>> +
>> +	/*
>> +	 * cclkin: source clock of mmc controller.
>> +	 * bus_hz: card interface clock generated by CLKGEN.
>> +	 * bus_hz = cclkin / RK3288_CLKGEN_DIV;
>> +	 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
>> +	 *
>> +	 * Note: div can only be 0 or 1
>> +	 *       if DDR50 8bit mode, div must be set 1
>> +	 */
>> +	if ((ios->bus_width == MMC_BUS_WIDTH_8) &&
>> +	    (ios->timing == MMC_TIMING_UHS_DDR50 ||
>> +	     ios->timing == MMC_TIMING_MMC_DDR52))
>> +		cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
>> +	else
>> +		cclkin = ios->clock * RK3288_CLKGEN_DIV;
>> +
>> +	ret = clk_set_rate(host->ciu_clk, cclkin);
>> +	if (ret)
>> +		dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
>> +
>> +	host->bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
>> +}
>> +
>> +static const struct dw_mci_drv_data rk2928_drv_data = {
>> +	.prepare_command	= dw_mci_pltfm_prepare_command,
>> +};
>> +
>> +static const struct dw_mci_drv_data rk3288_drv_data = {
>>  	.prepare_command	= dw_mci_pltfm_prepare_command,
>> +	.set_ios	= dw_mci_rk3288_set_ios,
>> +	.setup_clock	= dw_mci_rk3288_setup_clock,
>>  };
>>  
>>  static const struct dw_mci_drv_data socfpga_drv_data = {
>> @@ -95,7 +139,9 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
>>  static const struct of_device_id dw_mci_pltfm_match[] = {
>>  	{ .compatible = "snps,dw-mshc", },
>>  	{ .compatible = "rockchip,rk2928-dw-mshc",
>> -		.data = &rockchip_drv_data },
>> +		.data = &rk2928_drv_data },
>> +	{ .compatible = "rockchip,rk3288-dw-mshc",
>> +		.data = &rk3288_drv_data },
>>  	{ .compatible = "altr,socfpga-dw-mshc",
>>  		.data = &socfpga_drv_data },
>>  	{},
>>
> 
> 
> 
>