Re: [PATCH 3/7] drm/exynos: fimd: modify vclk calculation for I80 i/f

From: YoungJun Cho <yj44.cho@samsung.com>
To: Inki Dae <inki.dae@samsung.com>
Cc: sw0312.kim@samsung.com, dri-devel@lists.freedesktop.org,
	a.hajda@samsung.com, kyungmin.park@samsung.com
Subject: Re: [PATCH 3/7] drm/exynos: fimd: modify vclk calculation for I80 i/f
Date: Thu, 13 Nov 2014 18:54:13 +0900	[thread overview]
Message-ID: <54647FC5.8000307@samsung.com> (raw)
In-Reply-To: <546475EB.8070700@samsung.com>

Hi Inki,

On 11/13/2014 06:12 PM, Inki Dae wrote:
> On 2014년 10월 01일 15:19, YoungJun Cho wrote:
>> The I80 interface uses SYS_WE and SYS_CS to process
>> 1 pixel data, so it requires the twice faster clock
>> than the pixel clock.
>> And the frame done interrupt should occurr prior to
>> the next TE signal, H/W guy recommends to use as 1.73
>> times faster clock frequency.
>>
>> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
>> Acked-by: Inki Dae <inki.dae@samsung.com>
>> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
>>   drivers/gpu/drm/exynos/exynos_drm_fimd.c | 26 ++++++++++++++++++++------
>>   1 file changed, 20 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> index b2f6007..05c2a97a 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> @@ -81,6 +81,11 @@
>>   #define LCD_WR_HOLD(x)			((x) << 4)
>>   #define I80IFEN_ENABLE			(1 << 0)
>>
>> +/* I80 interface clock */
>> +#define I80_DATA_SAMPLING_CYCLE		2
>> +#define I80_TE_PERIOD_US		1667
>> +#define I80_DATA_TRANSACTION_TIME_US	964
>> +
>>   /* FIMD has totally five hardware windows. */
>>   #define WINDOWS_NR	5
>>
>> @@ -303,16 +308,25 @@ static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
>>   static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
>>   		const struct drm_display_mode *mode)
>>   {
>> -	unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
>> +	unsigned long ideal_clk;
>>   	u32 clkdiv;
>>
>>   	if (ctx->i80_if) {
>>   		/*
>> -		 * The frame done interrupt should be occurred prior to the
>> -		 * next TE signal.
>> +		 * The I80 interface uses SYS_WE and SYS_CS to process 1 pixel
>> +		 * data, so it requires the twice faster clock than the pixel
>> +		 * clock[I80_DATA_SAMPLING_CYCLE].
>> +		 * And the frame done interrupt should occurr prior to the next
>> +		 * TE signal, H/W guy recommends to use as 1.73 times faster
>> +		 * frequency[I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US].
>>   		 */
>> -		ideal_clk *= 2;
>> -	}
>> +		ideal_clk = mode->hdisplay * mode->vdisplay *
>> +				I80_DATA_SAMPLING_CYCLE *
>> +				I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US;
>
> How about using one constant directly?
>
> I.e.,
> #define RECOMMENDED_VAR	1.73
>
>   ... I80_DATA_SAMPLING_CYCLE * RECOMMENDED_VAR
>
> Is there any case that the te period and data transaction time should be
> changed?
>

At first time, I did.

But it made following build break :
   drivers/built-in.o: In function `fimd_commit':
   exynos_adc.c:(.text+0x878bc): undefined reference to `__aeabi_ui2d'
   exynos_adc.c:(.text+0x878d0): undefined reference to `__aeabi_dmul'
   exynos_adc.c:(.text+0x878d4): undefined reference to `__aeabi_d2uiz'
   make: *** [vmlinux] Error 1

It came from using floating point value.
So I changed it.

Do you have any good idea ?

Thank you.
Best regards YJ

>
> Thanks,
> Inki Dae
>
>
>> +	} else
>> +		ideal_clk = mode->htotal * mode->vtotal;
>> +
>> +	ideal_clk *= mode->vrefresh;
>>
>>   	/* Find the clock divider value that gets us closest to ideal_clk */
>>   	clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
>> @@ -431,7 +445,7 @@ static void fimd_commit(struct exynos_drm_manager *mgr)
>>   		val |= VIDCON0_CLKSEL_LCD;
>>
>>   	clkdiv = fimd_calc_clkdiv(ctx, mode);
>> -	if (clkdiv > 1)
>> +	if (clkdiv >= 1)
>>   		val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
>>
>>   	writel(val, ctx->regs + VIDCON0);
>>
>
>

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