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From: Deepak <deepak.s@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 06/15] drm/i915: Move VLV/CHV prepare_pll later
Date: Mon, 17 Aug 2015 10:09:41 +0530	[thread overview]
Message-ID: <55D1658D.5000903@linux.intel.com> (raw)
In-Reply-To: <1436388361-11130-7-git-send-email-ville.syrjala@linux.intel.com>



On 07/09/2015 02:15 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With DPIO powergating active on CHV, we can't even access the DPIO PLL
> registers until the lane power state overrides have been enabled. That
> will happen from the encoder .pre_pll_enable() hook, so move
> chv_prepare_pll() to happen after that point, which puts it just before
> chv_enable_pll() actually.
>
> Do the same for VLV to avoid accumulating weird differences between the
> platforms. Both platforms seem happy with the new arrangement.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 14 +++++---------
>   1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0473b38..666a236 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5979,13 +5979,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>   
>   	is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>   
> -	if (!is_dsi) {
> -		if (IS_CHERRYVIEW(dev))
> -			chv_prepare_pll(intel_crtc, intel_crtc->config);
> -		else
> -			vlv_prepare_pll(intel_crtc, intel_crtc->config);
> -	}
> -
>   	if (intel_crtc->config->has_dp_encoder)
>   		intel_dp_set_m_n(intel_crtc, M1_N1);
>   
> @@ -6009,10 +6002,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>   			encoder->pre_pll_enable(encoder);
>   
>   	if (!is_dsi) {
> -		if (IS_CHERRYVIEW(dev))
> +		if (IS_CHERRYVIEW(dev)) {
> +			chv_prepare_pll(intel_crtc, intel_crtc->config);
>   			chv_enable_pll(intel_crtc, intel_crtc->config);
> -		else
> +		} else {
> +			vlv_prepare_pll(intel_crtc, intel_crtc->config);
>   			vlv_enable_pll(intel_crtc, intel_crtc->config);
> +		}
>   	}
>   
>   	for_each_encoder_on_crtc(dev, crtc, encoder)
Looks fine to me
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
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  parent reply	other threads:[~2015-08-17  4:42 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-08 20:45 [PATCH 00/15] drm/i915: CHV DPIO power gating, take two ville.syrjala
2015-07-08 20:45 ` [PATCH 01/15] drm/i915: Always program m2 fractional value on CHV ville.syrjala
2015-08-17  2:19   ` Deepak
2015-08-17 11:45     ` Ville Syrjälä
2015-08-26  8:11       ` Deepak
2015-07-08 20:45 ` [PATCH 02/15] drm/i915: Always program unique transition scale for CHV ville.syrjala
2015-08-17  2:31   ` Deepak
2015-07-08 20:45 ` [PATCH 03/15] drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there ville.syrjala
2015-08-17  4:16   ` Deepak
2015-08-17 11:53     ` Ville Syrjälä
2015-08-26  8:14       ` Deepak
2015-07-08 20:45 ` [PATCH 04/15] drm/i915: Move DPIO port init earlier ville.syrjala
2015-08-17  4:18   ` Deepak
2015-07-08 20:45 ` [PATCH 05/15] drm/i915: Add locking around chv_phy_control_init() ville.syrjala
2015-08-17  4:23   ` Deepak
2015-07-08 20:45 ` [PATCH 06/15] drm/i915: Move VLV/CHV prepare_pll later ville.syrjala
2015-08-17  4:36   ` Deepak
2015-08-17  4:39   ` Deepak [this message]
2015-07-08 20:45 ` [PATCH 07/15] drm/i915: Add vlv_dport_to_phy() ville.syrjala
2015-08-17  4:56   ` Deepak
2015-08-26  8:24   ` Daniel Vetter
2015-07-08 20:45 ` [PATCH 08/15] drm/i915: Implement PHY lane power gating for CHV ville.syrjala
2015-08-19  1:48   ` Deepak
2015-08-26  8:27   ` Daniel Vetter
2015-07-08 20:45 ` [PATCH 09/15] drm/i915: Trick CL2 into life on CHV when using pipe B with port B ville.syrjala
2015-08-19  2:17   ` Deepak
2015-08-19 11:29     ` Ville Syrjälä
2015-08-26 12:36       ` Daniel Vetter
2015-07-08 20:45 ` [PATCH 10/15] drm/i915: Force common lane on for the PPS kick on CHV ville.syrjala
2015-07-10  7:56   ` [PATCH v2 " ville.syrjala
2015-08-19  2:21   ` [PATCH " Deepak
2015-08-19 11:32     ` Ville Syrjälä
2015-07-08 20:45 ` [PATCH 11/15] drm/i915: Enable DPIO SUS clock gating " ville.syrjala
2015-08-19 13:09   ` Deepak
2015-07-08 20:45 ` [PATCH 12/15] drm/i915: Force CL2 off in CHV x1 PHY ville.syrjala
2015-08-19 13:22   ` Deepak
2015-08-19 13:39     ` Ville Syrjälä
2015-08-26 12:38       ` Daniel Vetter
2015-07-08 20:45 ` [PATCH 13/15] drm/i915: Clean up CHV lane soft reset programming ville.syrjala
2015-07-09 16:27   ` Daniel Vetter
2015-07-09 17:14   ` [PATCH v2 " ville.syrjala
2015-08-27  4:25   ` [PATCH " Deepak
2015-07-08 20:46 ` [PATCH 14/15] drm/i915: Add some CHV DPIO lane power state asserts ville.syrjala
2015-08-27  4:36   ` Deepak
2015-08-27 11:02     ` Ville Syrjälä
2015-08-31 10:47       ` Deepak
2015-07-08 20:46 ` [PATCH 15/15] drm/i915: Add CHV PHY LDO power sanity checks ville.syrjala
2015-08-27  4:39   ` Deepak
2015-09-01  9:45     ` Daniel Vetter
2015-07-09 13:24 ` [PATCH 00/15] drm/i915: CHV DPIO power gating, take two Deepak

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