From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 08/21] drm/i915: Use HWS for seqno tracking everywhere
Date: Mon, 6 Jun 2016 15:55:18 +0100 [thread overview]
Message-ID: <57558ED6.5030304@linux.intel.com> (raw)
In-Reply-To: <1464970133-29859-9-git-send-email-chris@chris-wilson.co.uk>
On 03/06/16 17:08, Chris Wilson wrote:
> By using the same address for storing the HWS on every platform, we can
> remove the platform specific vfuncs and reduce the get-seqno routine to
> a single read of a cached memory location.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_trace.h | 2 +-
> drivers/gpu/drm/i915/intel_breadcrumbs.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 26 +---------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 83 ++++++++------------------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +--
> 9 files changed, 36 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0c287bf0d230..72dae6fb0aa2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -662,7 +662,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
> engine->name,
> i915_gem_request_get_seqno(work->flip_queued_req),
> dev_priv->next_seqno,
> - engine->get_seqno(engine),
> + intel_engine_get_seqno(engine),
> i915_gem_request_completed(work->flip_queued_req));
> } else
> seq_printf(m, "Flip not associated with any ring\n");
> @@ -792,7 +792,7 @@ static void i915_ring_seqno_info(struct seq_file *m,
> struct rb_node *rb;
>
> seq_printf(m, "Current sequence (%s): %x\n",
> - engine->name, engine->get_seqno(engine));
> + engine->name, intel_engine_get_seqno(engine));
> seq_printf(m, "Current user interrupts (%s): %x\n",
> engine->name, READ_ONCE(engine->user_interrupts));
>
> @@ -1417,7 +1417,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
>
> for_each_engine_id(engine, dev_priv, id) {
> acthd[id] = intel_ring_get_active_head(engine);
> - seqno[id] = engine->get_seqno(engine);
> + seqno[id] = intel_engine_get_seqno(engine);
> }
>
> i915_get_extra_instdone(dev_priv, instdone);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b0460eda2113..4a71f4e9a97a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3221,13 +3221,13 @@ i915_seqno_passed(uint32_t seq1, uint32_t seq2)
>
> static inline bool i915_gem_request_started(const struct drm_i915_gem_request *req)
> {
> - return i915_seqno_passed(req->engine->get_seqno(req->engine),
> + return i915_seqno_passed(intel_engine_get_seqno(req->engine),
> req->previous_seqno);
> }
>
> static inline bool i915_gem_request_completed(const struct drm_i915_gem_request *req)
> {
> - return i915_seqno_passed(req->engine->get_seqno(req->engine),
> + return i915_seqno_passed(intel_engine_get_seqno(req->engine),
> req->seqno);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 89241ffcc676..81341fc4e61a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -983,7 +983,7 @@ static void i915_record_ring_state(struct drm_i915_private *dev_priv,
> ering->waiting = intel_engine_has_waiter(engine);
> ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
> ering->acthd = intel_ring_get_active_head(engine);
> - ering->seqno = engine->get_seqno(engine);
> + ering->seqno = intel_engine_get_seqno(engine);
> ering->last_seqno = engine->last_submitted_seqno;
> ering->start = I915_READ_START(engine);
> ering->head = I915_READ_HEAD(engine);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2a736f4a0fe5..4013ad92cdc6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2951,7 +2951,7 @@ static int semaphore_passed(struct intel_engine_cs *engine)
> if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
> return -1;
>
> - if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
> + if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
Should be signaller, not engine, by the look of it.
> return 1;
>
> /* cursory check for an unkickable deadlock */
> @@ -3139,7 +3139,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> engine->irq_seqno_barrier(engine);
>
> acthd = intel_ring_get_active_head(engine);
> - seqno = engine->get_seqno(engine);
> + seqno = intel_engine_get_seqno(engine);
>
> /* Reset stuck interrupts between batch advances */
> user_interrupts = 0;
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index 6768db032f84..3d13fde95fdf 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -558,7 +558,7 @@ TRACE_EVENT(i915_gem_request_notify,
> TP_fast_assign(
> __entry->dev = engine->i915->dev->primary->index;
> __entry->ring = engine->id;
> - __entry->seqno = engine->get_seqno(engine);
> + __entry->seqno = intel_engine_get_seqno(engine);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u",
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index e0121f727938..44346de39794 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -148,7 +148,7 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
> first = true;
> parent = NULL;
> completed = NULL;
> - seqno = engine->get_seqno(engine);
> + seqno = intel_engine_get_seqno(engine);
>
> p = &b->waiters.rb_node;
> while (*p) {
> @@ -275,7 +275,7 @@ void intel_engine_remove_wait(struct intel_engine_cs *engine,
> * the first_waiter. This is undesirable if that
> * waiter is a high priority task.
> */
> - u32 seqno = engine->get_seqno(engine);
> + u32 seqno = intel_engine_get_seqno(engine);
> while (i915_seqno_passed(seqno, to_wait(next)->seqno)) {
> struct rb_node *n = rb_next(next);
> __intel_breadcrumbs_finish(b, to_wait(next));
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 270409e9ac7a..e48687837a95 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1712,16 +1712,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> return 0;
> }
>
> -static u32 gen8_get_seqno(struct intel_engine_cs *engine)
> -{
> - return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
> -}
> -
> -static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
> -{
> - intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
> -}
> -
> static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
> {
> /*
> @@ -1737,14 +1727,6 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
> intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
> }
>
> -static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
> -{
> - intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
> -
> - /* See bxt_a_get_seqno() explaining the reason for the clflush. */
> - intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
> -}
> -
> /*
> * Reserve space for 2 NOOPs at the end of each request to be
> * used as a workaround for not being allowed to do lite
> @@ -1770,7 +1752,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
> intel_hws_seqno_address(request->engine) |
> MI_FLUSH_DW_USE_GTT);
> intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
> + intel_logical_ring_emit(ringbuf, request->seqno);
> intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
> intel_logical_ring_emit(ringbuf, MI_NOOP);
> return intel_logical_ring_advance_and_submit(request);
> @@ -1916,12 +1898,8 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> engine->irq_get = gen8_logical_ring_get_irq;
> engine->irq_put = gen8_logical_ring_put_irq;
> engine->emit_bb_start = gen8_emit_bb_start;
> - engine->get_seqno = gen8_get_seqno;
> - engine->set_seqno = gen8_set_seqno;
> - if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> engine->irq_seqno_barrier = bxt_a_seqno_barrier;
> - engine->set_seqno = bxt_a_set_seqno;
> - }
> }
>
> static inline void
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 95f04345d3ec..bac496902c6d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1281,19 +1281,17 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> return ret;
>
> for_each_engine_id(waiter, dev_priv, id) {
> - u32 seqno;
> u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> - seqno = i915_gem_request_get_seqno(signaller_req);
> intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
> intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
> PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_CS_STALL);
> intel_ring_emit(signaller, lower_32_bits(gtt_offset));
> intel_ring_emit(signaller, upper_32_bits(gtt_offset));
> - intel_ring_emit(signaller, seqno);
> + intel_ring_emit(signaller, signaller_req->seqno);
> intel_ring_emit(signaller, 0);
> intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
> MI_SEMAPHORE_TARGET(waiter->hw_id));
> @@ -1322,18 +1320,16 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> return ret;
>
> for_each_engine_id(waiter, dev_priv, id) {
> - u32 seqno;
> u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> - seqno = i915_gem_request_get_seqno(signaller_req);
> intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
> MI_FLUSH_DW_OP_STOREDW);
> intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
> MI_FLUSH_DW_USE_GTT);
> intel_ring_emit(signaller, upper_32_bits(gtt_offset));
> - intel_ring_emit(signaller, seqno);
> + intel_ring_emit(signaller, signaller_req->seqno);
> intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
> MI_SEMAPHORE_TARGET(waiter->hw_id));
> intel_ring_emit(signaller, 0);
> @@ -1364,11 +1360,9 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
>
> if (i915_mmio_reg_valid(mbox_reg)) {
> - u32 seqno = i915_gem_request_get_seqno(signaller_req);
> -
> intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit_reg(signaller, mbox_reg);
> - intel_ring_emit(signaller, seqno);
> + intel_ring_emit(signaller, signaller_req->seqno);
> }
> }
>
> @@ -1404,7 +1398,7 @@ gen6_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
> intel_ring_emit(engine,
> I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> - intel_ring_emit(engine, i915_gem_request_get_seqno(req));
> + intel_ring_emit(engine, req->seqno);
> intel_ring_emit(engine, MI_USER_INTERRUPT);
> __intel_ring_advance(engine);
>
> @@ -1543,7 +1537,9 @@ static int
> pc_render_add_request(struct drm_i915_gem_request *req)
> {
> struct intel_engine_cs *engine = req->engine;
> - u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 addr = engine->status_page.gfx_addr +
> + (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> + u32 scratch_addr = addr;
> int ret;
Before my time. :)
Why was this code flushing all that space but above where it was
writting the seqno?
With this change it is flushing the seqno area as well.
>
> /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
> @@ -1559,12 +1555,12 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> return ret;
>
> intel_ring_emit(engine,
> - GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> + GFX_OP_PIPE_CONTROL(4) |
> + PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_WRITE_FLUSH |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
> - intel_ring_emit(engine,
> - engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> - intel_ring_emit(engine, i915_gem_request_get_seqno(req));
> + intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(engine, req->seqno);
> intel_ring_emit(engine, 0);
> PIPE_CONTROL_FLUSH(engine, scratch_addr);
> scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
> @@ -1579,13 +1575,12 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> PIPE_CONTROL_FLUSH(engine, scratch_addr);
>
> intel_ring_emit(engine,
> - GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> + GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_WRITE_FLUSH |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
> PIPE_CONTROL_NOTIFY);
> - intel_ring_emit(engine,
> - engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> - intel_ring_emit(engine, i915_gem_request_get_seqno(req));
> + intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(engine, req->seqno);
> intel_ring_emit(engine, 0);
> __intel_ring_advance(engine);
>
> @@ -1617,30 +1612,6 @@ gen6_seqno_barrier(struct intel_engine_cs *engine)
> spin_unlock_irq(&dev_priv->uncore.lock);
> }
>
> -static u32
> -ring_get_seqno(struct intel_engine_cs *engine)
> -{
> - return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
> -}
> -
> -static void
> -ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
> -{
> - intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
> -}
> -
> -static u32
> -pc_render_get_seqno(struct intel_engine_cs *engine)
> -{
> - return engine->scratch.cpu_page[0];
> -}
> -
> -static void
> -pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
> -{
> - engine->scratch.cpu_page[0] = seqno;
> -}
> -
> static bool
> gen5_ring_get_irq(struct intel_engine_cs *engine)
> {
> @@ -1770,8 +1741,8 @@ i9xx_add_request(struct drm_i915_gem_request *req)
>
> intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
> intel_ring_emit(engine,
> - I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> - intel_ring_emit(engine, i915_gem_request_get_seqno(req));
> + I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> + intel_ring_emit(engine, req->seqno);
> intel_ring_emit(engine, MI_USER_INTERRUPT);
> __intel_ring_advance(engine);
>
> @@ -2588,7 +2559,9 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> memset(engine->semaphore.sync_seqno, 0,
> sizeof(engine->semaphore.sync_seqno));
>
> - engine->set_seqno(engine, seqno);
> + intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
> + if (engine->irq_seqno_barrier)
> + engine->irq_seqno_barrier(engine);
> engine->last_submitted_seqno = seqno;
>
> engine->hangcheck.seqno = seqno;
> @@ -2830,8 +2803,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->irq_get = gen8_ring_get_irq;
> engine->irq_put = gen8_ring_put_irq;
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> if (i915_semaphore_is_enabled(dev_priv)) {
> WARN_ON(!dev_priv->semaphore_obj);
> engine->semaphore.sync_to = gen8_ring_sync;
> @@ -2848,8 +2819,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->irq_put = gen6_ring_put_irq;
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> if (i915_semaphore_is_enabled(dev_priv)) {
> engine->semaphore.sync_to = gen6_ring_sync;
> engine->semaphore.signal = gen6_signal;
> @@ -2874,8 +2843,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> } else if (IS_GEN5(dev_priv)) {
> engine->add_request = pc_render_add_request;
> engine->flush = gen4_render_ring_flush;
> - engine->get_seqno = pc_render_get_seqno;
> - engine->set_seqno = pc_render_set_seqno;
> engine->irq_get = gen5_ring_get_irq;
> engine->irq_put = gen5_ring_put_irq;
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
> @@ -2886,8 +2853,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> engine->flush = gen2_render_ring_flush;
> else
> engine->flush = gen4_render_ring_flush;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> if (IS_GEN2(dev_priv)) {
> engine->irq_get = i8xx_ring_get_irq;
> engine->irq_put = i8xx_ring_put_irq;
> @@ -2965,8 +2930,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->flush = gen6_bsd_ring_flush;
> engine->add_request = gen6_add_request;
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> if (INTEL_GEN(dev_priv) >= 8) {
> engine->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
> @@ -3004,8 +2967,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> engine->mmio_base = BSD_RING_BASE;
> engine->flush = bsd_ring_flush;
> engine->add_request = i9xx_add_request;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> if (IS_GEN5(dev_priv)) {
> engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> engine->irq_get = gen5_ring_get_irq;
> @@ -3040,8 +3001,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
> engine->flush = gen6_bsd_ring_flush;
> engine->add_request = gen6_add_request;
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> engine->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
> engine->irq_get = gen8_ring_get_irq;
> @@ -3073,8 +3032,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> engine->flush = gen6_ring_flush;
> engine->add_request = gen6_add_request;
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
> if (INTEL_GEN(dev_priv) >= 8) {
> engine->irq_enable_mask =
> GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
> @@ -3133,8 +3090,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> engine->flush = gen6_ring_flush;
> engine->add_request = gen6_add_request;
> engine->irq_seqno_barrier = gen6_seqno_barrier;
> - engine->get_seqno = ring_get_seqno;
> - engine->set_seqno = ring_set_seqno;
>
> if (INTEL_GEN(dev_priv) >= 8) {
> engine->irq_enable_mask =
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 061088360b80..785c9e5312ff 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -219,9 +219,6 @@ struct intel_engine_cs {
> * monotonic, even if not coherent.
> */
> void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
> - u32 (*get_seqno)(struct intel_engine_cs *ring);
> - void (*set_seqno)(struct intel_engine_cs *ring,
> - u32 seqno);
> int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
> u64 offset, u32 length,
> unsigned dispatch_flags);
> @@ -497,6 +494,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
> int intel_init_vebox_ring_buffer(struct drm_device *dev);
>
> u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
> +static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
> +{
> + return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
> +}
>
> int init_workarounds_ring(struct intel_engine_cs *engine);
>
>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-06-06 14:55 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-03 16:08 Breadcrumbs, again Chris Wilson
2016-06-03 16:08 ` [PATCH 01/21] drm/i915/shrinker: Flush active on objects before counting Chris Wilson
2016-06-03 16:08 ` [PATCH 02/21] drm/i915: Delay queuing hangcheck to wait-request Chris Wilson
2016-06-08 8:42 ` Daniel Vetter
2016-06-08 9:13 ` Chris Wilson
2016-06-03 16:08 ` [PATCH 03/21] drm/i915: Remove the dedicated hangcheck workqueue Chris Wilson
2016-06-06 12:52 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 04/21] drm/i915: Make queueing the hangcheck work inline Chris Wilson
2016-06-03 16:08 ` [PATCH 05/21] drm/i915: Separate GPU hang waitqueue from advance Chris Wilson
2016-06-06 13:00 ` Tvrtko Ursulin
2016-06-07 12:11 ` Arun Siluvery
2016-06-03 16:08 ` [PATCH 06/21] drm/i915: Slaughter the thundering i915_wait_request herd Chris Wilson
2016-06-06 13:58 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 07/21] drm/i915: Spin after waking up for an interrupt Chris Wilson
2016-06-06 14:39 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 08/21] drm/i915: Use HWS for seqno tracking everywhere Chris Wilson
2016-06-06 14:55 ` Tvrtko Ursulin [this message]
2016-06-08 9:24 ` Chris Wilson
2016-06-03 16:08 ` [PATCH 09/21] drm/i915: Stop mapping the scratch page into CPU space Chris Wilson
2016-06-06 15:03 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 10/21] drm/i915: Allocate scratch page from stolen Chris Wilson
2016-06-06 15:05 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 11/21] drm/i915: Refactor scratch object allocation for gen2 w/a buffer Chris Wilson
2016-06-06 15:09 ` Tvrtko Ursulin
2016-06-08 9:27 ` Chris Wilson
2016-06-03 16:08 ` [PATCH 12/21] drm/i915: Add a delay between interrupt and inspecting the final seqno (ilk) Chris Wilson
2016-06-03 16:08 ` [PATCH 13/21] drm/i915: Check the CPU cached value of seqno after waking the waiter Chris Wilson
2016-06-06 15:10 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 14/21] drm/i915: Only apply one barrier after a breadcrumb interrupt is posted Chris Wilson
2016-06-06 15:34 ` Tvrtko Ursulin
2016-06-08 9:35 ` Chris Wilson
2016-06-08 9:57 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 15/21] drm/i915: Stop setting wraparound seqno on initialisation Chris Wilson
2016-06-08 8:54 ` Daniel Vetter
2016-06-03 16:08 ` [PATCH 16/21] drm/i915: Only query timestamp when measuring elapsed time Chris Wilson
2016-06-06 13:50 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 17/21] drm/i915: Convert trace-irq to the breadcrumb waiter Chris Wilson
2016-06-07 12:04 ` Tvrtko Ursulin
2016-06-08 9:48 ` Chris Wilson
2016-06-08 10:16 ` Tvrtko Ursulin
2016-06-08 11:24 ` Chris Wilson
2016-06-08 11:47 ` Tvrtko Ursulin
2016-06-08 12:34 ` Chris Wilson
2016-06-08 12:44 ` Tvrtko Ursulin
2016-06-08 13:47 ` Chris Wilson
2016-06-03 16:08 ` [PATCH 18/21] drm/i915: Embed signaling node into the GEM request Chris Wilson
2016-06-07 12:31 ` Tvrtko Ursulin
2016-06-08 9:54 ` Chris Wilson
2016-06-03 16:08 ` [PATCH 19/21] drm/i915: Move the get/put irq locking into the caller Chris Wilson
2016-06-07 12:46 ` Tvrtko Ursulin
2016-06-08 10:01 ` Chris Wilson
2016-06-08 10:18 ` Tvrtko Ursulin
2016-06-08 11:10 ` Chris Wilson
2016-06-08 11:49 ` Tvrtko Ursulin
2016-06-08 12:54 ` Chris Wilson
2016-06-03 16:08 ` [PATCH 20/21] drm/i915: Simplify enabling user-interrupts with L3-remapping Chris Wilson
2016-06-07 12:50 ` Tvrtko Ursulin
2016-06-03 16:08 ` [PATCH 21/21] drm/i915: Remove debug noise on detecting fault-injection of missed interrupts Chris Wilson
2016-06-07 12:51 ` Tvrtko Ursulin
2016-06-03 16:35 ` ✗ Ro.CI.BAT: failure for series starting with [01/21] drm/i915/shrinker: Flush active on objects before counting Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=57558ED6.5030304@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.