All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Souza, Jose" <jose.souza@intel.com>
To: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dhinakaran.pandiyan@gmail.com" <dhinakaran.pandiyan@gmail.com>
Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v2 1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function
Date: Mon, 30 Apr 2018 22:54:11 +0000	[thread overview]
Message-ID: <579376ca9bb221cd50b6ce856a6d98a2b1ba852b.camel@intel.com> (raw)
In-Reply-To: <1890796.p13hcCd3MI@dk>

On Wed, 2018-04-25 at 17:41 -0700, Dhinakaran Pandiyan wrote:
> On Wednesday, April 18, 2018 3:43:03 PM PDT José Roberto de Souza
> wrote:
> > It was reading some random register in VLV and CHV.
> > 
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > 
> > No changes from v1.
> > 
> >  drivers/gpu/drm/i915/intel_psr.c | 9 +++++----
> >  1 file changed, 5 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c index 69a5b276f4d8..659180656f5b
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -424,6 +424,11 @@ static void hsw_psr_activate(struct intel_dp
> > *intel_dp)
> > struct drm_device *dev = dig_port->base.base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > 
> > +	if (dev_priv->psr.psr2_enabled)
> > +		WARN_ON(I915_READ(EDP_PSR2_CTL) &
> > EDP_PSR2_ENABLE);
> > +	else
> > +		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> > +
> 
> Why not move the checks under hsw_activate_psr2 and
> hsw_activate_psr1?  This 
> is just duplicating another  psr2_enabled branch that is right below.

Okay, done.

> 
> >  	/* On HSW+ after we enable PSR on source it will activate
> > it
> >  	 * as soon as it match configure idle_frame count. So
> >  	 * we just actually enable it here on activation time.
> > @@ -549,10 +554,6 @@ static void intel_psr_activate(struct intel_dp
> > *intel_dp) struct drm_device *dev = intel_dig_port->base.base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > 
> > -	if (dev_priv->psr.psr2_enabled)
> > -		WARN_ON(I915_READ(EDP_PSR2_CTL) &
> > EDP_PSR2_ENABLE);
> > -	else
> > -		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> >  	WARN_ON(dev_priv->psr.active);
> >  	lockdep_assert_held(&dev_priv->psr.lock);
> 
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2018-04-30 22:54 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-18 22:43 [PATCH v2 1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function José Roberto de Souza
2018-04-18 22:43 ` [PATCH v2 2/9] drm/i915/psr: Move PSR exit specific code to hardware specific function José Roberto de Souza
2018-05-16  0:42   ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 3/9] drm/i915/psr: Remove intel_crtc_state parameter from disable() José Roberto de Souza
2018-04-19 11:18   ` Ville Syrjälä
2018-04-18 22:43 ` [PATCH v2 4/9] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink José Roberto de Souza
2018-04-26 22:29   ` Dhinakaran Pandiyan
2018-04-30 23:02     ` Souza, Jose
2018-04-18 22:43 ` [PATCH v2 5/9] drm/i915/psr: Handle PSR RFB storage error José Roberto de Souza
2018-04-26 22:37   ` Dhinakaran Pandiyan
2018-04-30 23:28     ` Souza, Jose
2018-05-08 22:16       ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 6/9] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side José Roberto de Souza
2018-04-20 21:16   ` Rodrigo Vivi
2018-04-25 21:02     ` Souza, Jose
2018-05-16  0:38   ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 7/9] drm/i915/dp: Move code to check if aux ch is busy to a function José Roberto de Souza
2018-04-26 22:51   ` Dhinakaran Pandiyan
2018-04-30 23:39     ` Souza, Jose
2018-05-08 21:29       ` Pandiyan, Dhinakaran
2018-04-18 22:43 ` [PATCH v2 8/9] drm/i915/dp: Improve intel_dp_aux_is_busy() José Roberto de Souza
2018-05-08 22:10   ` Dhinakaran Pandiyan
2018-04-18 22:43 ` [PATCH v2 9/9] drm/i915/dp: Avoid concurrent access when HW is using aux ch José Roberto de Souza
2018-04-18 22:48 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/9] drm/i915/psr: Move specific HSW+ WARN_ON to HSW+ function Patchwork
2018-04-18 22:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-04-18 23:09 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-19  0:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-26  0:41 ` [PATCH v2 1/9] " Dhinakaran Pandiyan
2018-04-30 22:54   ` Souza, Jose [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=579376ca9bb221cd50b6ce856a6d98a2b1ba852b.camel@intel.com \
    --to=jose.souza@intel.com \
    --cc=dhinakaran.pandiyan@gmail.com \
    --cc=dhinakaran.pandiyan@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.