From: Richard Henderson <richard.henderson@linaro.org>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, qemu-devel@nongnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v7 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Date: Tue, 31 Aug 2021 09:19:43 -0700 [thread overview]
Message-ID: <60dcad53-de32-2527-86e8-41be6219cb35@linaro.org> (raw)
In-Reply-To: <20210830111511.1905048-10-philipp.tomsich@vrull.eu>
On 8/30/21 4:15 AM, Philipp Tomsich wrote:
> + TCGv tmp = tcg_temp_new();
> +
> + /* Set msb in each byte if the byte was zero. */
> + tcg_gen_subi_tl(tmp, source1, dup_const(MO_8, 0x01));
> + tcg_gen_andc_tl(tmp, tmp, source1);
> + tcg_gen_andi_tl(tmp, tmp, dup_const(MO_8, 0x80));
> +
> + /* Replicate the msb of each byte across the byte. */
> + tcg_gen_shri_tl(tmp, tmp, 7);
> + tcg_gen_muli_tl(tmp, tmp, 0xff);
> +
> + /* Negate */
> + tcg_gen_not_tl(ret, tmp);
It just occurred to me that we can swap the shift/andi and re-use the same constant, and
we can fold in the negate with andc.
TCGv ones = tcg_constant_tl(dup_const(MO_8, 1));
TCGv tmp = tcg_temp_new();
tcg_gen_sub_tl(tmp, src1, ones);
tcg_gen_andc_tl(tmp, tmp, src1);
tcg_gen_shri_tl(tmp, tmp, 7);
tcg_gen_andc_tl(tmp, ones, tmp);
tcg_gen_muli_tl(tmp, tmp, 0xff);
tcg_temp_free(tmp);
r~
next prev parent reply other threads:[~2021-08-31 16:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-30 11:14 [PATCH v7 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-30 11:14 ` [PATCH v7 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 02/14] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 04/14] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 06/14] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 07/14] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 08/14] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-08-31 0:21 ` Alistair Francis
2021-08-31 16:19 ` Richard Henderson [this message]
2021-08-30 11:15 ` [PATCH v7 10/14] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 11/14] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 13/14] target/riscv: Remove RVB (replaced by Zb[abcs] Philipp Tomsich
2021-08-30 11:15 ` [PATCH v7 14/14] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
2021-09-02 2:26 ` Alistair Francis
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