From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, vandana.kannan@intel.com
Subject: Re: [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation
Date: 07 May 2015 14:22:45 -0700 [thread overview]
Message-ID: <6299f3$ljujhe@orsmga002.jf.intel.com> (raw)
In-Reply-To: <1430980259-5471-2-git-send-email-vandana.kannan@intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6340
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 316/316 316/316
IVB 342/342 342/342
BYT 286/286 286/286
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-05-07 21:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-07 6:30 [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Vandana Kannan
2015-05-07 6:30 ` [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation Vandana Kannan
2015-05-07 13:07 ` Imre Deak
2015-05-13 6:50 ` [PATCH v2 " Vandana Kannan
2015-05-18 16:28 ` Imre Deak
2015-05-19 8:04 ` Daniel Vetter
2015-05-07 21:22 ` shuang.he [this message]
2015-05-07 9:27 ` [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Imre Deak
2015-05-11 14:39 ` Kannan, Vandana
2015-05-13 6:48 ` [PATCH v3 " Vandana Kannan
2015-05-18 16:26 ` Imre Deak
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