From: Luca Tettamanti <kronos.it@gmail.com>
To: Dave Airlie <airlied@gmail.com>
Cc: dri-devel@lists.sf.net
Subject: Re: [PATCH] [rfc] drm/radeon/kms: pm debugging check for vbl.
Date: Tue, 23 Feb 2010 22:38:58 +0100 [thread overview]
Message-ID: <68676e01002231338i1ff7b3edw7e5006fc63f1bd43@mail.gmail.com> (raw)
In-Reply-To: <21d7e9971002180229r40f7b10cra329566f35467039@mail.gmail.com>
2010/2/18 Dave Airlie <airlied@gmail.com>:
> 2010/2/18 Rafał Miłecki <zajec5@gmail.com>:
>> W dniu 18 lutego 2010 09:28 użytkownik Dave Airlie <airlied@gmail.com> napisał:
>>>>
>>>>> It adds some reading & printing steps before every reclock, while we
>>>>> really want it to happen as soon as possible. Maybe you could execute
>>>>> this only on some
>>>
>>> btw you won't get the print if you are in vblank, and if you aren't
>>> well the print
>>> doesn't matter, I'm also thinking the engine change reads/writes a lot of regs,
>>> so two more might not matter so much.
>>
>> Yeah, maybe that's right.
>>
>> While your idea of testing being in VBLANK is "sane" :) it could
>> happen we start reclocking in VBLANK (first test will pass), we
>> reclock out of VBLANK (not wanted, possible corruption), and we hit
>> next VBLANK in second test.
>>
>> In such situation (machine) I'm sure we will hit "false" in test
>> anyway (sooner or later) but maybe we could improve in anyway somehow?
>> To make sure it's sill the same VBLANK?
>
> That could be possible, though if a reclock takes a full scanout to
> operate we've
> got other issues as it would never be possible by the sounds of it.
I might be seeing something like this O_o
[ 257.583603] [drm] not in vbl for pm change 00020002 00000000 at entry
[ 257.583609] [drm] Setting: e: 22000 m: 30000 p: 16
(no warning at exit)
I have wait queue fix in place... I also see some unsynched reclocks.
On a somewhat unrelated note the current clock selection code does not
work well with the tables defined on my card (M76):
[ 156.577741] ATOM BIOS: ASUS_F3Sa
[ 156.577794] [drm] Clocks initialized !
[ 156.577833] [drm] 5 Power State(s)
[ 156.577871] [drm] State 0 Default (default)
[ 156.577909] [drm] 16 PCIE Lanes
[ 156.577946] [drm] 3 Clock Mode(s)
[ 156.577984] [drm] 0 engine/memory: 220000/300000
[ 156.578023] [drm] 1 engine/memory: 220000/300000
[ 156.578063] [drm] 2 engine/memory: 220000/300000
[ 156.578102] [drm] State 1 Performance
[ 156.578139] [drm] 16 PCIE Lanes
[ 156.578177] [drm] 3 Clock Mode(s)
[ 156.578214] [drm] 0 engine/memory: 220000/252000
[ 156.578253] [drm] 1 engine/memory: 220000/300000
[ 156.578292] [drm] 2 engine/memory: 500000/400000
[ 156.578332] [drm] State 2 Battery
[ 156.578369] [drm] 16 PCIE Lanes
[ 156.578406] [drm] 3 Clock Mode(s)
[ 156.578444] [drm] 0 engine/memory: 220000/252000
[ 156.578483] [drm] 1 engine/memory: 220000/252000
[ 156.578522] [drm] 2 engine/memory: 220000/300000
[ 156.578561] [drm] State 3 Performance
[ 156.578599] [drm] 16 PCIE Lanes
[ 156.578636] [drm] 3 Clock Mode(s)
[ 156.578674] [drm] 0 engine/memory: 300000/400000
[ 156.578713] [drm] 1 engine/memory: 300000/400000
[ 156.578752] [drm] 2 engine/memory: 500000/400000
[ 156.578791] [drm] State 4 Battery
[ 156.578828] [drm] 16 PCIE Lanes
[ 156.578866] [drm] 3 Clock Mode(s)
[ 156.578903] [drm] 0 engine/memory: 220000/300000
[ 156.578942] [drm] 1 engine/memory: 220000/300000
[ 156.578981] [drm] 2 engine/memory: 220000/300000
radeon_pick_power_state with a mobility chip only uses battery and
powersave states.
Luca
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prev parent reply other threads:[~2010-02-23 21:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-18 6:50 [PATCH] [rfc] drm/radeon/kms: pm debugging check for vbl Dave Airlie
2010-02-18 8:04 ` Rafał Miłecki
2010-02-18 8:16 ` Dave Airlie
2010-02-18 8:28 ` Dave Airlie
2010-02-18 10:12 ` Rafał Miłecki
2010-02-18 10:29 ` Dave Airlie
2010-02-23 21:38 ` Luca Tettamanti [this message]
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